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Numerical modelling of the delamination in multi-layered ceramic capacitor during the thermal reflow process

Fei Chong Ng, Aizat Abas, Mohamad Riduwan Ramli, Mohamad Fikri Mohd Sharif, Fakhrozi Che Ani

Soldering & Surface Mount Technology

ISSN: 0954-0911

Article publication date: 20 October 2022

Issue publication date: 21 April 2023

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Abstract

Purpose

This paper aims to study the interfacial delamination found in the boundary of the copper/copper-epoxy layers of a multi-layer ceramic capacitor.

Design/methodology/approach

The thermal reflow process of the capacitor assembly and the crack propagation from the initial micro voids presented in the boundary, and later manifested into delamination, were numerically simulated. Besides, the cross section of the capacitor assembly was inspected for delamination cracks and voids using a scanning electronic microscope.

Findings

Interfacial delamination in the boundary of copper/copper-epoxy layers was caused by the thermal mismatch and growth of micro voids during the thermal reflow process. The maximum deformation on the capacitor during reflow was 2.370 µm. It was found that a larger void would induce higher vicinity stress, mode I stress intensity factor, and crack elongation rate. Moreover, the crack extension increased with the exerted deformation until 0.3 µm, before saturating at the peak crack extension of around 0.078 µm.

Practical implications

The root cause of interfacial delamination issues in capacitors due to thermal reflow has been identified, and viable solutions proposed. These can eliminate the additional manufacturing cost and lead time incurred in identifying and tackling the issues; as well as benefit end-users, by promoting the electronic device reliability and performance.

Originality/value

To the best of the authors’ knowledge, the mechanism of delamination occurrence in a capacitor during has not been reported to date. The parametric variation analysis of the void size and deformation on the crack growth has never been conducted.

Keywords

Acknowledgements

This research work was partly supported by the following grants: BJIM Matching Grant (Grant No.: 1001.PMEKANIK.8070022) and USM-WD CiA Lab Grant (Grant No.: 311/PMEKANIK/4402055).

Citation

Ng, F.C., Abas, A., Ramli, M.R., Mohd Sharif, M.F. and Che Ani, F. (2023), "Numerical modelling of the delamination in multi-layered ceramic capacitor during the thermal reflow process", Soldering & Surface Mount Technology, Vol. 35 No. 3, pp. 166-174. https://doi.org/10.1108/SSMT-03-2022-0017

Publisher

:

Emerald Publishing Limited

Copyright © 2022, Emerald Publishing Limited

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