Mansour Assaf, Salema Khan, Sunil Das and Satyendra Biswas
The energy optimization techniques developed for conventional ad hoc networks do not appropriately address the unique features of the wireless embedded sensor networks (WESNs). In…
Abstract
The energy optimization techniques developed for conventional ad hoc networks do not appropriately address the unique features of the wireless embedded sensor networks (WESNs). In the WESN environment, only reducing the overall energy consumption is not considered enough to maximize the life span of the entire network, but maintaining full network connectivity for a sufficiently long period of time is also an important design goal due to the energy constraints of each node. The wireless radio is a major energy user and is often the focus of energy conservation mechanisms, since the nodes communicate in a shared medium (air interface). The medium access control (MAC) layer of the communication protocol stack arbitrates access to the communications link by manipulating the sleep, listen, transmit, and receive states of the radio transceivers. The bursty traffic networks experience long periods of inactivity interrupted by unplanned and often short lived periods of high traffic loads. Currently available MAC protocols cannot meet application fidelity requirements of the bursty traffic networks since they are designed either for networks with periodic traffic or are not sufficiently traffic-adaptive, thereby introducing large multi-hop latency delays to realize network connectivity, overprovision during light traffic conditions, and slow ramp up at the initiation of a high traffic episode. This paper presents enhancements made to the energy efficient MAC protocol which is especially designed for the bursty traffic networks and in the process targets some available communication techniques used in the WESNs for discussion and comparison.
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Tariq Syed, Sunil Das, Satyendra Biswas, Mansour Assaf and Emil Petriu
The requirement for an automated test system has immensely increased due to the realization that manual testing is associated with additional resources and staffing constraints…
Abstract
The requirement for an automated test system has immensely increased due to the realization that manual testing is associated with additional resources and staffing constraints. In order to achieve a competitive edge, reduced development cost, timely product delivery, and product quality are mandatory in today's organization. Manual testing requires skilled operators that increase cost, time, and product delivery. The low cost computer-based automated system helps to get an edge by fulfilling these organizational demands. In this paper, an automated testing system has been developed to support functional testing of all phases of Nortel Networks 1-Meg modem system as its system under test (SUT). The modem is an inherently complex asymmetric digital subscriber line (ADSL) product and its testing is far more complex than just verification of process faults. The complexity of ADSL system renders automated test system an important and imperative part of ADSL testing. The subject paper demonstrates the indispensable need of automated test system for ADSL testing and its relative advantages in providing some benefit for the organization.
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Sunil Das, Liwu Jin, Mansour Assaf, Satyendra Biswas and Emil Petriu
The implementation of fault testing environment for embedded cores-based digital circuits is a challenging endeavor. The subject paper aims developing techniques in design…
Abstract
The implementation of fault testing environment for embedded cores-based digital circuits is a challenging endeavor. The subject paper aims developing techniques in design verification and test architecture utilizing well-known concepts of hardware and software co-design. There are available methods to ensure correct functionality, in both hardware and software, for embedded cores-based systems but one of the most used and acceptable approaches to realize this is through the use of design-for-testability (DFT). Specifically, applications of built-in self-test (BIST) methodology in testing embedded cores are considered in the paper, with specific implementations being targeted towards the International Symposium on Circuits and Systems (ISCAS) 85 combinational benchmark circuits.
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Sunil Das, Satyendra Biswas, Emil Petriu, Voicu Groza, Mansour Assaf and Amiya Nayak
The design of space-efficient support hardware for built-in self-testing (BIST) is of immense significance in the synthesis of present day very large-scale integration (VLSI…
Abstract
The design of space-efficient support hardware for built-in self-testing (BIST) is of immense significance in the synthesis of present day very large-scale integration (VLSI) circuits and systems, particularly in the context of design paradigm shift from system-on-board to system-on-chip (SOC). This paper presents an overview of the general problem of designing zero-aliasing or aliasing-free space compression hardware in relation to embedded cores-based SOC for single stuck-line faults in particular, extending the well-known concepts of conventional switching theory, and of incompatibility relation to generate maximal compatibility classes (MCCs) utilizing graph theory concepts, based on optimal generalized sequence mergeability, as developed by the authors in earlier works. The paper briefly presents the mathematical basis of selection criteria for merger of an optimal number of outputs of the module under test (MUT) for realizing maximum compaction ratio in the design, along with extensive simulation results on International Symposium on Circuits and Systems or ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits, with simulation programs ATALANTA, FSIM, and COMPACTEST.
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Mansour Assaf, Leslie-Ann Moore, Sunil Das, Satyendra Biswas and Scott Morton
A low-level logic fault test simulation environment targeted towards application-specific integrated circuits (ASICs) in particular is proposed in this paper. The simulation…
Abstract
A low-level logic fault test simulation environment targeted towards application-specific integrated circuits (ASICs) in particular is proposed in this paper. The simulation environment emulates a typical built-in self-testing (BIST) environment with test pattern generator (TPG) that sends its outputs to a circuit (core) under test (CUT) and the output streams from the CUT are fed into an output response analyzer (ORA). The developed simulator is very suitable for testing embedded digital intellectual property (IP) cores-based systems. The paper describes the total test architecture environment, including the application of the logic fault simulator. Results on simulation on some specific International Symposium on Circuits and Systems (ISCAS) 85 combinational and ISCAS 89 sequential benchmark circuits are provided as well for appraisal.
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Sunil Das, Alexander Applegate, Satyendra Biswas and Emil Petriu
The design of aliasing-free space support hardware for built-in self-testing in very large scale integration circuits and systems is of immense significance, specifically due to…
Abstract
The design of aliasing-free space support hardware for built-in self-testing in very large scale integration circuits and systems is of immense significance, specifically due to the design paradigm shift in recent years from system-on-board to system-on-chip. This paper discusses approach to realizing aliasing-free space compaction hardware targeting particularly embedded cores-based system-on-chips for single stuck-line faults, extending well-known concept from conventional switching theory, viz. that of compatibility relation as used in the minimization of incompletely specified sequential machines. For a pair of response outputs of the circuit under test, the method introduces the notion of fault detection compatibility and conditional fault detection compatibility (conditional upon some other response output pair being simultaneously fault detection compatible) with respect to two-input AND/NAND, OR/NOR and XOR/XNOR logic, respectively. The process is illustrated with design details of space compactors for the International Symposium on Circuits and Systems or ISCAS 85 combinational (and ISCAS 89 full-scan sequential) benchmark circuits using simulation programs ATALANTA and FSIM, attesting to the relevance of the technique from the viewpoint of simplicity, resultant low area overhead and full fault coverage for single stuck-line faults, thereby making it an appropriate choice in commercial design environments.
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Sunil Das, Satyendra Biswas, Voicu Groza and Mansour Assaf
Realizing aliasing-free space compressor for built-in self-testing of very large scale integration circuits and systems is of immense practical significance, especially due to the…
Abstract
Realizing aliasing-free space compressor for built-in self-testing of very large scale integration circuits and systems is of immense practical significance, especially due to the design paradigm shift in recent years from system-on-board to system-on-chip. This paper explores and provides new results on extending the scope of a recently developed approach to synthesizing aliasing-free space compaction hardware targeting particularly embedded cores-based system-on-chips for single stuck-line faults. For a pair of response outputs of the circuit under test, the method uses the notion of fault detection compatibility and conditional fault detection compatibility (conditional upon some other response output pair being simultaneously fault detection compatible) with respect to two-input AND/NAND nonlinear logic. The process is illustrated with development details of space compressors for the International Symposium on Circuits and Systems or ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits (results on full-scan sequential circuits though not included in the paper) using simulation programs ATALANTA and FSIM, showing the relevance of the technique from the viewpoint of simplicity, resultant low area overhead and full fault coverage for single stuck-line faults, thereby making it an ideal choice in actual design environments.
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With the growing acceptance of renewable energy sources in the world, new energy sources are pursued and investigated by customers. In India, residential PV technology is in an…
Abstract
Purpose
With the growing acceptance of renewable energy sources in the world, new energy sources are pursued and investigated by customers. In India, residential PV technology is in an early stage of development and very less in demand among households. Therefore, the purpose of this study is to identify the major variables and its impact on customers purchase intention towards solar PV technology, especially in the context of central India.
Design/methodology/approach
Based on literature reviews, this study identifies six major independent variables having a relationship with purchase intentions. Using convenience sampling method, 413 customers’ data has been collected by the researcher and was investigated through structural equation modelling, using SmartPLS 2.0 and SPSS-20 software.
Findings
The study findings suggested that the construct promotional strategies, societal influence, customer awareness and government initiative plays an important role in generating customers purchase intention towards solar PV technology. While the constructs environmental concern and availability & cost having relationship, showed insignificant influence.
Research limitations/implications
The study outcomes provide some valuable insights to the government and policymakers in designing their policies and strategies to increase customer involvement in solar PV technology. This study suggested that the service providers need to offer more benefits in the form of subsidies and schemes that motivate customers to willingly show their purchase intention.
Originality/value
The major contribution of this study is the empirical analysis of six independent variables, which affects the customer purchase intentions towards solar PV technology over available conventional energy sources in an emerging Indian market.
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Abid Haleem, Bisma Mannan, Sunil Luthra, Sanjay Kumar and Sonal Khurana
Technology forecasting (TF) and assessment (TA), all in all, apply to any intentional and deliberate endeavours to forecast and view the potential heading, rate, attributes and…
Abstract
Purpose
Technology forecasting (TF) and assessment (TA), all in all, apply to any intentional and deliberate endeavours to forecast and view the potential heading, rate, attributes and impacts of technological change, especially for development, advancement, selection and utilisation of resources, which ultimately helps in the benchmarking. A vast variety of methods are available for TF and TA. Till now, practically, no exertion has been made to choose proper, satisfactory innovation methods or technology. The paper aims to discuss this issue.
Design/methodology/approach
In this paper, there is an endeavour to summarise the vast field of TF and TA, through its evolution, functions, applications and techniques. This paper provides the in-depth review of the utilisation of TF and TA methodologies and its improvement, which helps the users in selecting the appropriate method of TF and TA for a specific situation.
Findings
This study concludes that the quest for a single strategy for doing forecast and assessment is a misconception. This neglects to perceive that forecast and assessment oblige a suitable blend of strategies and methods drawn from a variety of fields. Researchers and practitioners must be innovative, imperative and specialised in choosing TF and TA methodologies, and cannot be programmed.
Practical implications
The technology seems to be the most significant driver of the present day global developments. Some technologies have far-reaching implications, and the authors need to understand these issues regarding its’ forecasting and its assessment.
Originality/value
The decision of proper worthy procedure amid a circumstance may have an impact on the exactness and reliability of the forecast and assessment. Significant observations regarding learning, action/s, actor/s and expected outcomes are discussed.
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Insha Kousar Kalem, Z.F. Bhat, Sunil Kumar and Reshan Mudiyanselage Jayawardena
The purpose of this study was to assess the preservative potential of Tinospora cordifolia as a novel natural preservative in muscle foods.
Abstract
Purpose
The purpose of this study was to assess the preservative potential of Tinospora cordifolia as a novel natural preservative in muscle foods.
Design/methodology/approach
Chevon sausages were used as a model system and were prepared by incorporating different levels of T. cordifolia, namely, T1 (0.25 per cent), T2 (0.50 per cent) and T3 (0.75 per cent), and assessed for lipid oxidative stability and storage quality under refrigerated (4 ± 10°C) conditions.
Findings
Lipid oxidative stability showed a significant improvement as the products incorporated with T. cordifolia exhibited significantly (p = 0.001) lower thiobarbituric acid reacting substances (mg malonaldehyde/kg) in comparison to control. A significant improvement was also observed in the microbial stability as T. cordifolia-incorporated products showed significantly lower values for total plate count (log cfu/g, p = 0.001), psychrophilic count (log cfu/g, p = 0.003), yeast and mould count (log cfu/g, p = 0.02) and free fatty acid (percentage of oleic acid, p = 0.01). Significantly higher scores were observed for various sensory parameters of the treated products during storage.
Originality/value
Tinospora cordifolia successfully improved the lipid oxidative and microbial stability of the model meat product and may be commercially exploited as a novel preservative in muscle foods.