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Implementing built-in self-test environment for cores-based digital circuits with Verilog HDL

Sunil Das, Liwu Jin, Mansour Assaf, Satyendra Biswas, Emil Petriu

World Journal of Engineering

ISSN: 1708-5284

Article publication date: 21 January 2013

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Abstract

The implementation of fault testing environment for embedded cores-based digital circuits is a challenging endeavor. The subject paper aims developing techniques in design verification and test architecture utilizing well-known concepts of hardware and software co-design. There are available methods to ensure correct functionality, in both hardware and software, for embedded cores-based systems but one of the most used and acceptable approaches to realize this is through the use of design-for-testability (DFT). Specifically, applications of built-in self-test (BIST) methodology in testing embedded cores are considered in the paper, with specific implementations being targeted towards the International Symposium on Circuits and Systems (ISCAS) 85 combinational benchmark circuits.

Keywords

Citation

Das, S., Jin, L., Assaf, M., Biswas, S. and Petriu, E. (2013), "Implementing built-in self-test environment for cores-based digital circuits with Verilog HDL", World Journal of Engineering, Vol. 9 No. 6, pp. 519-528. https://doi.org/10.1260/1708-5284.9.6.519

Publisher

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Emerald Group Publishing Limited

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