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Pink ring is a ubiquitous problem arising during the manufacture of multilayer PCBs, being the manifestation of local delamination at the inner‐layer oxide interfaces around drilled holes and subsequent dissolution of the oxide during plating processes. Except in extreme cases, there is no evidence that the occurrence of pink ring identifies any in‐service reliability problem, but it is nevertheless a clear process indicator and is strictly monitored in statistical process control. The UK Printed Circuit Industry has carried out a collaborative research programme aimed at providing an understanding and a quantitative analysis of the pink ring condition. The research has advanced on two fronts: (i) an investigation into the micro‐mechanisms of the delamination and stress relief around drilled holes and subsequent rôles of the desmear and plating chemicals, and (ii) a statistical analysis of boards manufactured in a variety of ways, analysing the quantitative measurements of pink ring in terms of, for example, panel source, drill supplier, drill quality, drilling backing material, drilling chip rate, stack position, and panel entry/exit side.

In future generations, electronic systems will rely extensively on advanced IC technology to achieve higher performance levels. However, with limits placed on the level of integration that can be obtained on a single IC, a need still exists for an interconnection hierarchy to provide the necessary density transform between system components. A recent addition to many high performance interconnection structures has been the Multichip Module. By eliminating the conventional IC package, MCMs have dramatically reduced the electrical length between devices, thereby minimising propagation delay, crosstalk, and attenuation. Although MCM techniques will offer many performance advantages, they also present many design challenges at subsequent levels of interconnection. This paper will focus on the requirements of MCM backplanes interconnecting several modules and, as a solution, will present recent work on advanced metal core substrates. MCM substrates provide a tremendous density advantage, however, the interconnection between modules is still a formidable task. Modules often have I/O densities of 300 to 500 leads per square inch and typically dissipate 10 to 50 watts per square inch. In addition, with sub‐nanosecond rise times, the distance between modules is often sufficient for signal paths to be treated as transmission lines. In an effort to meet these requirements, metal core circuits based on copper, copper Invar, and copper molybdenum have been fabricated using 0·0025 in. diameter embedded discrete wiring technology. Combined with a Kevlar surface layer suitable for wire bonding and blind laser drilled vias to access the internal wires, this technique offers many benefits. As many as 4 conductors can pass between holes on 0·050 in. centres in a single wiring layer only 0·018 in. thick. With the absence of interstitial vias, additional substrate area can be dedicated to create a sizeable thermal path, essential to conduct the heat from the MCM to an internal metal core. Together, these features have made this an attractive approach for interconnecting multichip modules.

In the never‐ending quest for speed, designers are now turning to digital GaAs integrated circuits both to extend the bandwidth of current designs and in some cases to generate a whole new class of products never before possible. The engineer well versed in high speed ECL design techniques generally understands the problems associated with this transfer to GaAs logic. However, even with the design task well defined, the exact solution for interconnecting devices is often difficult and stresses the capabilities of existing multilayer printed circuit techniques using conventional dielectric materials and processing. This paper examines the design task in detail, and will present recent developments in shielded discrete wiring techniques as a possible solution for GaAs packaging.

Flex‐rigid circuits have been used for many years, primarily by the military, as a method to reduce the size and increase the reliability of electronic systems. However, in today's emerging designs where high speed ASICs are often the dominant components, flex‐rigid circuit assemblies are now an attractive solution for providing high density transmission line interconnects from board to board. Much of today's circuitry is being committed to ASIC designs to increase both circuit density and speed. Following this path, designers are faced with the task of interconnecting high lead count SMT packages often with as many as 300 to 500 leads per device, each dissipating several watts. At these power densities conductive cooling through the circuit board is often a necessity, dictating the use of either metal cores or heat exchangers. To make efficient use of the core and minimise weight, designs generally require SMT packages to be mounted on both sides of the core with electrical communication from side to side. However, as more exotic core materials (carbon fibre matrix, beryllium, etc.) and liquid cooled heat exchangers are used, electrical communication through the core has become difficult, if not impossible, in some cases. Instead, high density flex‐rigid assemblies are used to partition the circuit, allowing the board to ‘fold’ over the core. This results in hundreds of signal lines that must cross the flex, obeying the electrical design rules dictated by the rigid sections to maintain impedance values and crosstalk margins. This paper focuses on recent work at AIT, producing high density flex‐rigid circuits using embedded discrete wiring technology to meet the above requirements. Using 0.0025 in. diameter polyimide insulated wire, as many as 100 lines per linear inch can pass over the flex region on a single layer. This generally results in a single flex layer where all wires can be referenced to a continuous ground plane from board to board. Controlled impedance is easily maintained due to the uniform wire geometry, and high frequency attenuation is significantly lower than on equivalent etch circuit designs due to the smooth surface finish on the wire. In addition, the high interconnection density offered by this technique reduces the overall thickness of the rigid sections, thereby minimising the thermal resistance to the core.

The purpose of this paper is to describe the current state of the research field of business process architecture (BPA) and its design methodologies.

A systematic literature review (SLR) was conducted using meta- and content-based perspectives.

From over 6,000 candidate studies, 89 were selected. A fifth of these primary works corresponded to BPA design methodologies. Though the BPA research field remains in an early stage of development, it bears promising growth potential. Regarding BPA design methodologies, the following aspects susceptible for further research were detected: identification and modeling of business process relationships; specification of inputs; standardization of models, notations and tool support; consideration of managerial concerns; integration of knowledge from other areas; and validation of methodological and product quality aspects.

The main limitation of the work lies in not being fully reproducible due to the fixed number of data sources and their digital nature, together with subjective decisions in work selection, data extraction and data analysis.

To the best of the authors’ knowledge no study has yet analyzed the BPA research field by means of an SLR. This study will benefit practitioners and research groups working on this topic by allowing them to get a rigorous overview of the BPA research field with an emphasis on available BPA design methodologies, and become aware of research gaps within the BPA field to position further research.

Increasing speeds combined with the level of integration that can be obtained with advanced IC technology has dramatically changed the interconnection requirements for high performance electronic systems. With much of today's circuitry being implemented in custom silicon, IC technology has allowed both a dramatic reduction in size and a tremendous increase in performance. However, in terms of the interconnection problem, the by‐product of advanced IC technology is a new generation of IC s that often require several hundred I/OS, exhibit rise times of 150 ps to 300 ps, and dissipate several watts per device. As demanding requirements are placed upon circuit boards, the complexity of the design task increases dramatically, since a working solution must simultaneously address interconnection density, signal integrity and thermal performance. This paper examines embedded discrete wiring technology as a high density solution that meets the requirements necessary for transporting high speed digital signals.

Discussion of religion and education continues to evoke conceptions of confessional teaching; however, research and educational practices in recent decades illustrate an expanded understanding that relates to the teaching of, about, and from religion across formal and non-formal educational spaces in secular and religious spheres. An expanded understanding also illustrates various intersections between religion and education that extend beyond religious or non-sectarian instruction, to include everything from the recognition and accommodation of religious student identities in K-12 public school settings, to the internationalization of religious higher education. Drawing on the Comparative and International Education Society’s Religion & Education Special Interest Group’s programing and activities, this paper aims to present a brief summary of trends observed both in research and practice concerning religion and education among educators worldwide, and highlights the place of religion in our growing recognition of intersectionality, one that occurs between academics and the community.