The purpose of this paper is to focus on through‐silicon via (TSV), with a new concept that every chip or interposer could have two surfaces with circuits. Emphasis is placed on…
Abstract
Purpose
The purpose of this paper is to focus on through‐silicon via (TSV), with a new concept that every chip or interposer could have two surfaces with circuits. Emphasis is placed on the 3D IC integration, especially the interposer (both active and passive) technologies and their roadmaps. The origin of 3D integration is also briefly presented.
Design/methodology/approach
This design addresses the electronic packaging of 3D IC integration with a passive TSV interposer for high‐power, high‐performance, high pin‐count, ultra fine‐pitch, small real‐estate, and low‐cost applications. To achieve this, the design uses chip‐to‐chip interconnections through a passive TSV interposer in a 3D IC integration system‐in‐package (SiP) format with excellent thermal management.
Findings
A generic, low‐cost and thermal‐enhanced 3D IC integration SiP with a passive interposer has been proposed for high‐performance applications. Also, the origin of 3D integration and the overview and outlook of 3D Si integration and 3D IC integration have been presented and discussed. Some important results and recommendations are summarized: the TSV/redistribution layer (RDL)/integrated passive devices passive interposer, which supports the high‐power chips on top and low‐power chips at its bottom, is the gut and workhorse of the current 3D IC integration design; with the passive interposer, it is not necessary to “dig” holes on the active chips. In fact, try to avoid making TSVs in the active chips; the passive interposer provides flexible coupling for whatever chips are available and/or necessary, and enhances the functionality and possibly the routings (shorter); with the passive interposer, the TSV manufacturing cost is lower because the requirement of TSV manufacturing yield is too high (>99.99 percent) for the active chips to bear additional costs due to TSV manufacturing yield loss; with the passive interposer, wafer thinning and thin‐wafer handling costs (for the interposer) are lower because these are not needed for the active chips and thus adds no cost due to yield loss; with the current designs, all the chips are bare; the packaging cost for individual chips is eliminated; more than 90 percent of heat from the 3D IC integration SiP is dissipated from the backside of high‐power chips using a thermal interface material and heat spreader/sink; the appearance and footprint of current 3D IC integration SiP designs are very attractive to integrated device manufactures, original equipment manufactures, and electronics manufacturing services (EMS) because they are standard packages; and underfills between the copper‐filled TSV interposer and the high‐ and low‐power chips are recommended to reduce creep damage of the lead‐free microbump solder joints and prolong their lives.
Originality/value
The paper's findings will be very useful to the electronic industry.
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An exact analysis is presented for the creep deformation of solder interconnects subjected to the actions of bending moment, twisting moment and axial force. Dimensionless…
Abstract
An exact analysis is presented for the creep deformation of solder interconnects subjected to the actions of bending moment, twisting moment and axial force. Dimensionless interaction curves and charts which relate the variables, interconnect geometry, solder material properties, axial force, bending moment, twisting moment, bending stress, shearing stress, curvature rate and twist rate are also provided for engineering practice convenience. The constitutive relationship of the 96.5Sn3.5Ag solder interconnects is described by the Garofalo‐Arrhenius steady‐state creep equation.
Dilupa Nakandala, Henry Lau and Jingjing Zhang
Logistics practitioners must continually improve inventory management processes as they daily respond to the twin drivers of customer satisfaction and cost efficiency. The purpose…
Abstract
Purpose
Logistics practitioners must continually improve inventory management processes as they daily respond to the twin drivers of customer satisfaction and cost efficiency. The purpose of this paper is to investigate the scenario of sourcing goods through lateral transshipments in a periodic-review policy setting, against a backdrop of cost optimization objectives.
Design/methodology/approach
The authors develop decision rules that make cost-optimized selection between backordering and combined reactive and proactive lateral transshipment options possible. This necessarily takes account of the trade-off between purchasing, holding and backorder cost components. In addition, the authors use simulation studies to illustrate the superior performance of the proposed decision options.
Findings
According to results of the simulation studies, the proposed two-step decision rule generates the lower inventory cost than the alternative decisions rules. The outperformance of proposed two-step decision rule is valid in different scenario.
Practical implications
This study develops the decision rules to assist wholesaler logistics practitioners to make optimized decisions with regard to whether they should proactively lateral transshipments and if selected, the optimum size of the extra lateral transshipment.
Originality/value
This study has made a significant contribution to the existing knowledge base as it develops decision rules for a combined proactive and reactive approach using lateral transhipments to meet both urgent demand and a part of the demand expected during the supplier lead time in a cost-efficient way.
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The solder‐joint reliability of solder‐bumped wafer level chip scale package (WLCSP) on microvia build‐up printed circuit board (PCB) subjected to thermal cycling conditions is…
Abstract
The solder‐joint reliability of solder‐bumped wafer level chip scale package (WLCSP) on microvia build‐up printed circuit board (PCB) subjected to thermal cycling conditions is investigated in this study. The 62Sn36Pb2Ag solder joints are assumed to be: an elastic material; an elastic‐plastic material; and a creep material which obey the Garofalo‐Arrhenius steady‐state creep constitutive law. The stress and strain in the corner solder joint of the WLCSP assembly are presented and compared for these three material models. Also, the results presented herein will be compared with that from creep analysis of the WLCSP on PCB without microvia build‐up layer.
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Chun Sean Lau, C.Y. Khor, D. Soares, J.C. Teixeira and M.Z. Abdullah
The purpose of the present study was to review the thermo-mechanical challenges of reflowed lead-free solder joints in surface mount components (SMCs). The topics of the review…
Abstract
Purpose
The purpose of the present study was to review the thermo-mechanical challenges of reflowed lead-free solder joints in surface mount components (SMCs). The topics of the review include challenges in modelling of the reflow soldering process, optimization and the future challenges in the reflow soldering process. Besides, the numerical approach of lead-free solder reliability is also discussed.
Design/methodology/approach
Lead-free reflow soldering is one of the most significant processes in the development of surface mount technology, especially toward the miniaturization of the advanced SMCs package. The challenges lead to more complex thermal responses when the PCB assembly passes through the reflow oven. The virtual modelling tools facilitate the modelling and simulation of the lead-free reflow process, which provide more data and clear visualization on the particular process.
Findings
With the growing trend of computer power and software capability, the multidisciplinary simulation, such as the temperature and thermal stress of lead-free SMCs, under the influenced of a specific process atmosphere can be provided. A simulation modelling technique for the thermal response and flow field prediction of a reflow process is cost-effective and has greatly helped the engineer to eliminate guesswork. Besides, simulated-based optimization methods of the reflow process have gained popularity because of them being economical and have reduced time-consumption, and these provide more information compared to the experimental hardware. The advantages and disadvantages of the simulation modelling in the reflow soldering process are also briefly discussed.
Practical implications
This literature review provides the engineers and researchers with a profound understanding of the thermo-mechanical challenges of reflowed lead-free solder joints in SMCs and the challenges of simulation modelling in the reflow process.
Originality/value
The unique challenges in solder joint reliability, and direction of future research in reflow process were identified to clarify the solutions to solve lead-free reliability issues in the electronics manufacturing industry.
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Several finite element models were proposed to investigate the effects of voids and their interactions on SMT solder joint reliability in thermal mismatch loading. Both linear…
Abstract
Several finite element models were proposed to investigate the effects of voids and their interactions on SMT solder joint reliability in thermal mismatch loading. Both linear elastic analysis and non‐linear and time‐dependent finite element analysis were performed on models with different sizes and locations of voids in solder joints. The focus was on the interactions of the two voids. Various distances between voids are considered. Constitutive equations accounting for both plasticity and creep for one solder material were assumed and implemented in a finite element program. The following observations have been obtained: (i) the stress and strain in a solder joint of two voids are different from those of a one void joint; (ii) the stress and strain reach a maximum for a particular void size and location either along the interface of the solder joint or at the edges of voids; (iii) the initiation of interfacial debonding may be induced by the interaction of the voids; (iv) creep due to thermal cycling has a significant effect on solder joint reliability.
J. Lau, Y.‐H. Pao, C. Larner, R. Govila, S. Twerefour, D. Gilbert, S. Erasmus and S. Dolot
The reliability of 0.4 mm pitch, 28 mm body size, 256‐pin plastic quad flat pack (QFP) no‐clean and water‐clean solder joints has been studied by temperature cycling and…
Abstract
The reliability of 0.4 mm pitch, 28 mm body size, 256‐pin plastic quad flat pack (QFP) no‐clean and water‐clean solder joints has been studied by temperature cycling and analytical analysis. The temperature cycling test was run non‐stop for more than 6 months, and the results have been presented as a Weibull distribution. A unique temperature cycling profile has been developed based on the calculated lead stiffness, elastic and creep strains in the solder joint, and solder data. Also, the thermal fatigue life of the solder joints has been estimated and correlated with experimental results. Furthermore, a failure analysis of the solder joints has been performed using scanning electron microscopy (SEM). Finally, a quantitative comparison between the no‐clean and water‐clean QFP solder joints has been presented.
J.H. Lau, S.J. Erasmus and D.W. Rice
A review of state‐of‐the‐art technology pertinent to tape automated bonding (for fine pitch, high I/O, high performance, high yield, high volume and high reliability) is…
Abstract
A review of state‐of‐the‐art technology pertinent to tape automated bonding (for fine pitch, high I/O, high performance, high yield, high volume and high reliability) is presented. Emphasis is placed on a new understanding of the key elements (for example, tapes, bumps, inner lead bonding, testing and burn‐in on tape‐with‐chip, encapsulation, outer lead bonding, thermal management, reliability and rework) of this rapidly moving technology.
Henry C. Lau, Andrew Ip, CKM Lee and GTS Ho
The purpose of this paper is to propose a three-tier assessment model (TAM), aiming to identify and evaluate the competitiveness level of companies. The existing problem is that…
Abstract
Purpose
The purpose of this paper is to propose a three-tier assessment model (TAM), aiming to identify and evaluate the competitiveness level of companies. The existing problem is that companies find it difficult to choose a proper model which can be deployed to benchmark with competitors in terms of their competiveness level in the marketplace. Most of the available models are not appropriate or easy to use. The proposed assessment model is able to provide an insight for better planning and preparation so as to gain a better chance of success comparing with their competitors. Most importantly, the proposal model adopts a pragmatic approach and can be implemented without going through tedious mathematical calculations and analysis.
Design/methodology/approach
TAM embraces three different approaches deployed in various stages of the application process. The first stage is to identify the relevant criteria using hierarchical holographic modeling and the second stage is to assess the associated weightings of these criteria used to rate the potential competitiveness of related companies. The technique used in stage two is known as fuzzy analytic hierarchy process (FAHP) which is a combination of two well-established methods including fuzzy logic and analytical hierarchical programming. In stage three, a technique known as technique for order preference by similarity to the ideal solution (TOPSIS) is adopted to benchmark the level of competitiveness covering several companies in the same industry.
Findings
In this paper, a case study is conducted in order to validate the feasibility and practicality of the proposed model. Results indicate that TAM can be easily applied in various industrial settings by practitioners in the field for supporting operations management practices.
Research limitations/implications
Significant amount of work is needed to ensure that the proposed model can be practically deployed in real industrial settings.
Practical implications
This proposed model is able to capitalize on the benefits of the HMM, FAHP and TOPSIS methods and offset their deficiencies. Most importantly, it can be applied to various industries without complex modification.
Originality/value
This paper suggests a hybrid model to assess competitiveness level embracing three different techniques with the unique feature which is able to provide an insight for better planning and preparation in order to excel competitors. Companies may be able to follow the procedures and steps suggested in the paper to implement the model which is proven to be pragmatic and can be applied in real situations.
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John H. Lau, Tony Chen and Tai‐Yu Chou
A family of cavity‐down plastic ball grid array (PBGA) packages have been designed by split via connection (SVC) and split wrap around (SWA) methods. Because of the special…
Abstract
A family of cavity‐down plastic ball grid array (PBGA) packages have been designed by split via connection (SVC) and split wrap around (SWA) methods. Because of the special designs, these packages consist of a single core of organic material and two‐metal layers of copper and are manufactured with the conventional printed circuit board (PCB) process at very low cost. The electrical performances of the packages are studied by both numerical simulations and experimental measurements. Parasitic parameters are extracted from time domain reflectometer (TDR) and time domain transmission (TDT) measurements. Cross‐talk and simultaneous switch output (SSO) noise of the packages are also investigated.