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This paper aims to present a robust prediction method for estimating the quality of electronic products assembled with pin-in-paste soldering technology. A specific board quality factor was also defined which describes the expected yield of the board assembly.

Experiments were performed to obtain the required input data for developing a prediction method based on decision tree learning techniques. A Type 4 lead-free solder paste (particle size 20–38 µm) was deposited by stencil printing with different printing speeds (from 20 mm/s to 70 mm/s) into the through-holes (0.8 mm, 1 mm, 1.1 mm, 1.4 mm) of an FR4 board. Hole-filling was investigated with X-ray analyses. Three test cases were evaluated.

The optimal parameters of the algorithm were determined as: subsample is 0.5, learning rate is 0.001, maximum tree depth is 6 and boosting iteration is 10,000. The mean absolute error, root mean square error and mean absolute percentage error resulted in 0.024, 0.03 and 3.5, respectively, on average for the prediction of the hole-filling value, based on the printing speed and hole-diameter after optimisation. Our method is able to predict the hole-filling in pin-in-paste technology for different through-hole diameters.

No research works are available in current literature regarding machine learning techniques for pin-in-paste technology. Therefore, we decided to develop a method using decision tree learning techniques for supporting the design of the stencil printing process for through-hole components and pin-in-paste technology. The first pass yield of the assembly can be enhanced, and the reflow soldering failures of pin-in-paste technology can be significantly reduced.

This paper aims to establish a more accurate model for lifetime estimation.

Finite element model simulation and experimental tests are used to enhance the lifetime prediction model of the solder joint.

A more precise model was found.

It is confirmed that the paper is original.

The purpose of this paper is to evaluate the effect of solder wettability on the thermal performance of a thermo‐electric cooler (TEC) of a 980 nm pump laser module.

In this paper, TEC thermal performance has been evaluated using a heat pump test. The results were compared with scanning acoustic microscopy (C‐SAM) results in order to have a better understanding of the thermal behaviour of the TEC. In the C‐SAM experiments, images were taken at the interfaces between the housing and TEC, as well as at the interfaces between the chip‐on‐carrier (CoC) and TEC.

The heat pump test results indicate a strong correlation with the C‐SAM test results. The C‐SAM observations show good solder joint at the interface between the TEC and housing in the case of the device that yielded a good heat pump test result (11.5°C) and poor solder joints (gross de‐lamination) at the interface between the TEC and housing in the case of the device that yielded a poor heat pump test result (24.4°C). The C‐SAM observations did not show much difference at the interface between the CoC and TEC. The results from this study were used to qualify the post‐vacuum soldered laser pump devices at JDS Uniphase, Plymouth, UK.

The findings presented in this paper indicate that the level of solder wettability at the interfaces between the piece parts impacts the thermal performance of the TEC.

The purpose of this paper is to find the optimum inverter type as the solder joint reliability point of view.

In this paper, finite element model(ing) simulations supported with power cycling aging experiments were used to demonstrate the best inverter type as the solder joint reliability point of view.

It was found that inverter types highly affect the solder joint health during its nominal operating.

The authors confirm the originality of this paper.

There are several lead-free solder alloys available in the industry. Over the years, the most favorable solder composition of tin-silver-copper (Sn-Ag-Cu [SAC]) has been vastly used and accepted for joining the electronic components. It is strongly believed that the silver (Ag) content has a significant impact on the solder mechanical behavior and thus solder thermal reliability performance. This paper aims to assess the mechanical response, i.e. creep response, of the SAC solder alloys with various Ag contents.

A three-dimensional nonlinear finite element simulation is used to investigate the thermal cyclic behavior of several SAC solder alloys with various silver percentages, including 1%, 2%, 3% and 4%. The mechanical properties of the unleaded interconnects with various Ag amounts are collected from reliable literature resources and used in the analysis accordingly. Furthermore, the solder creep behavior is examined using the two famous creep laws, namely, Garofalo’s and Anand’s models.

The nonlinear computational analysis results showed that the silver content has a great influence on the solder behavior as well as on thermal fatigue life expectancy. Specifically, solders with relatively high Ag content are expected to have lower plastic deformations and strains and thus better fatigue performance due to their higher strengths and failure resistance characteristics. However, such solders would have contrary fatigue performance in drop and shock environments and the low-Ag content solders are presumed to perform significantly better because of their higher ductility.

Generally, this research recommends the use of SAC solder interconnects of high silver contents, e.g. 3% and 4%, for designing electronic assemblies continuously exposed to thermal loadings and solders with relatively low Ag-content, i.e. 1% and 2%, for electronic packages under impact and shock loadings.

The purpose of the present study was to review the thermo-mechanical challenges of reflowed lead-free solder joints in surface mount components (SMCs). The topics of the review include challenges in modelling of the reflow soldering process, optimization and the future challenges in the reflow soldering process. Besides, the numerical approach of lead-free solder reliability is also discussed.

Lead-free reflow soldering is one of the most significant processes in the development of surface mount technology, especially toward the miniaturization of the advanced SMCs package. The challenges lead to more complex thermal responses when the PCB assembly passes through the reflow oven. The virtual modelling tools facilitate the modelling and simulation of the lead-free reflow process, which provide more data and clear visualization on the particular process.

With the growing trend of computer power and software capability, the multidisciplinary simulation, such as the temperature and thermal stress of lead-free SMCs, under the influenced of a specific process atmosphere can be provided. A simulation modelling technique for the thermal response and flow field prediction of a reflow process is cost-effective and has greatly helped the engineer to eliminate guesswork. Besides, simulated-based optimization methods of the reflow process have gained popularity because of them being economical and have reduced time-consumption, and these provide more information compared to the experimental hardware. The advantages and disadvantages of the simulation modelling in the reflow soldering process are also briefly discussed.

This literature review provides the engineers and researchers with a profound understanding of the thermo-mechanical challenges of reflowed lead-free solder joints in SMCs and the challenges of simulation modelling in the reflow process.

The unique challenges in solder joint reliability, and direction of future research in reflow process were identified to clarify the solutions to solve lead-free reliability issues in the electronics manufacturing industry.

Stencil cleaning is an important operation in solder paste printing process. Frequent cleaning may interrupt printing process and increase idle time, as well as loss for performing cleaning. This paper aims to propose a method to optimize the stencil cleaning time and reduce unnecessary cleaning operations and losses.

This paper uses a discrete-time, discrete-state homogeneous Markov chain to model the stencil printing performance degradation process, and the quality loss during the stencil printing process is estimated based on this degradation model. A stencil cleaning decision model based on renewal reward theorem is established, and the optimal cleaning time is obtained through a balance between quality loss and the loss on idle time.

A stencil cleaning decision model for solder paste printing is established, and numerical simulation results show that there exists an optimal stencil cleaning time which minimizes the long-term loss.

Stencil cleaning control is very important for solder paste printing. However, there are very few studies focusing on stencil cleaning control. This research contributes to developing a model to optimize the stencil cleaning time in solder paste printing process.

The purpose of this paper is to analyze and compare the mechanical properties of sintered nanosilver with different porosities at both the mesoscopic and macroscopic scales and to conduct a multiscale analysis of the porosity effect on the mechanical properties of sintered nanosilver.

This paper establishes a mesoscopic model for the uniaxial tension of sintered nanosilver and a macroscopic model for chips containing sintered silver layers. Using the finite element method, combined with crystal plasticity theory and unified creep plasticity theory, a multiscale analysis is conducted for the mechanical properties of sintered nanosilver. First, stress distribution characteristics under uniaxial tensile loading for different porosities in sintered nanosilver polycrystal models are analyzed at the mesoscopic scale. Second, at the macroscopic scale, the mechanical performance of sintered nanosilver layers with varying porosities in high-power chip models under cyclic loading is analyzed. Finally, the porosity influence on the damage evolution in sintered nanosilver is summarized, and simulations are conducted to explore the evolution of damage parameters in sintered nanosilver under different porosities.

In the mesoscopic model, the presence of mesoscale voids affects the stress distribution in sintered nanosilver subjected to tensile loading. Sintered nanosilver with lower porosity exhibits higher tensile strength. In the macroscopic model, sintered nanosilver layers with lower porosity correspond to a more uniform stress distribution, whereas higher porosity leads to faster accumulation of plastic strain in the sintered layer. During chip packaging processes, improving processes to reduce the porosity of sintered layers can delay the initiation of damage and the propagation of cracks in sintered nanosilver.

During chip packaging processes, improving processes to reduce the porosity of sintered layers can delay the initiation of damage and the propagation of cracks in sintered nanosilver.

This paper innovatively uses a mesoscopic crystal plasticity constitutive model and a macroscopic unified creep plasticity constitutive model to analyze the mechanical behavior of sintered nanosilver with different porosities. It comprehensively investigates and explains the influence of porosity on the mechanical performance of sintered nanosilver across multiple scales.

This study aims to present a more accurate lifetime prediction model considering solder chemical composition.

Thermal cycling and standard creep tests as well as finite element simulation were used.

The study found lower error in the solder joint lifetime evaluation. The higher the Ag content is, the higher the lifetime is achieved.

It is confirmed.

In microelectronics industry, the reliability of its components is a major area of concern for engineers. Therefore, it is imperative that such concerns are addressed by using the most reliable materials available. Thermal interface materials (TIMs) are used in electronic devices to bridge the topologies that exists between a heat sink and the flip chip assembly. Therefore, this study aims to investigate the reliability of SAC405 and SAC396 in a microelectronics assembly.

In this paper, SnAgCu solder alloys (SAC405 and SAC396) were used as the TIMs. The model, which comprises the chip, TIM and heat sink base, was developed with ANSYS finite element analysis software and simulated under a thermal cycling load of between −40°C and 85°C.

The results obtained from this paper were based on the total deformation, stress, strain and fatigue life of the lead-free solder materials. The analyses of the results showed that SAC405 is more reliable than SAC396. This was evident in the fatigue life analysis where it was predicted that it took about 85 days for SAC405 to fail, whereas it took about 13 days for SAC396 to fail. Therefore, SAC405 is recommended as the TIM of choice compared to SAC396 based upon the findings of this investigation.

This paper is centred on SnAgCu solders used as TIMs. This paper demonstrated that SAC405 is a reliable solder TIM. This can guide manufacturers of electronic products in deciding which SAC solder to apply as TIM during the assembly process.