Comparison between positive and negative bias stress on N‐channel VDMOSFET transistors

Abstract

Purpose

The purpose of this paper is to apply a negative gate bias stress in order to study instabilities of threshold voltage in N‐channel power vertical double‐diffused metal‐oxide‐semiconductor field effect transistor (VDMOSFET). Variations in gate oxide trapped charge and interface trap densities are also calculated.

Design/methodology/approach

A threshold voltage shift is detected; the oxide and interface trap densities were evaluated based on a direct measurement of the gate to source capacitance and conductance.

Findings

Results presented show that the threshold voltage is decreasing with stress time, the capacitance and conductance curves are altered by applied stress, also the oxide traps and the interface traps densities are increasing with stress time.

Originality/value

The positive bias stress seems to be more destructive in the case of the studied devices.

Citation

Abboud, N., Habch, R., Cuminal, Y., Foucaran, A. and Salame, C. (2013), "Comparison between positive and negative bias stress on N‐channel VDMOSFET transistors", International Journal of Structural Integrity, Vol. 4 No. 2, pp. 267-274. https://doi.org/10.1108/17579861311321735