Optimisation modelling for thermal fatigue reliability of lead‐free interconnects in fine‐pitch flip‐chip packaging

Abstract

Purpose

This paper aims to present an integrated optimisation‐modelling computational approach for virtual prototyping that helps design engineers to improve the reliability and performance of electronic components and systems through design optimisation at the early product development stage. The design methodology is used to identify the optimal design of lead‐free (Sn3.9Ag0.6Cu) solder joints in fine‐pitch copper column bumped flip‐chip electronic packages.

Design/methodology/approach

The design methodology is generic and comprises numerical techniques for computational modelling (finite element analysis) coupled with numerical methods for statistical analysis and optimisation. In this study, the integrated optimisation‐modelling design strategy is adopted to prototype virtually a fine‐pitch flip‐chip package at the solder interconnect level, so that the thermal fatigue reliability of the lead‐free solder joints is improved and important design rules to minimise the creep in the solder material, exposed to thermal cycling regimes, are formulated. The whole prototyping process is executed in an automated way once the initial design task is formulated and the conditions and the settings for the numerical analysis used to evaluate the flip‐chip package behaviour are specified. Different software modules that incorporate the required numerical techniques are used to identify the solution of the design optimisation problem related to solder joints reliability optimisation.

Findings

For fine‐pitch flip‐chip packages with copper column bumped die, it is found that higher solder joint volume and height of the copper column combined with lower copper column radius and solder wetting around copper column have a positive effect on the thermo‐mechanical reliability.

Originality/value

The findings of this research provide design rules for more reliable lead‐free solder joints for copper column bumped flip‐chip packages and help to establish further the technology as one of the viable routes for flip‐chip packaging.

Citation

Stoyanov, S., Bailey, C. and Desmulliez, M. (2009), "Optimisation modelling for thermal fatigue reliability of lead‐free interconnects in fine‐pitch flip‐chip packaging", Soldering & Surface Mount Technology, Vol. 21 No. 1, pp. 11-24. https://doi.org/10.1108/09540910910928265