Search results

The purpose of this study is to propose an analytical model with consideration of the permeability of soft-magnetic materials, which can predict the magnetic field distribution more accurately and facilitate the initial design and parameter optimization of the machine.

This paper proposes an analytical model of stator yokeless radial flux dual rotor permanent magnet synchronous machine (SYRFDR-PMSM) with the consideration of magnetic saturation of soft-magnetic material. The analytical model of SYRFDR-PMSM is divided into seven regions along the radial direction according to the different excitation source and magnetic medium, and the iron permeability in each region is considered based on the Maxwell–Fourier method and Cauchy’s product theorem. The magnetic vector potential of each region is obtained by the Laplace’s or Poisson’s equation, and the magnetic field solution is determined using the boundary conditions of adjacent regions.

The inner and outer air-gap flux density, flux linkage, output torque, etc., of SYRFDR-PMSM are predicted by analytical model, resulting in good agreement with that of finite element model. Additionally, the SYRFDR-PMSM prototype is manufactured and the correctness of analytical model is further verified by experiments on no-load back electromotive force and current–torque curve. Reasonable design of the slot opening width and pole arc coefficient can improve the average output torque and reduce output torque ripple.

The analytical model proposed in this paper assumes that the permeability of soft-magnetic material is a fixed value. However, the actual iron’s permeability varies nonlinearly; thus, the prediction results of the analytical model will have some deviations from the actual machine.

The main contribution of this paper is to propose an accurate magnetic field analytical model of SYRFDR-PMSM. It takes into account the permeability of soft-magnetic material and slot opening, which can quickly and accurately predict the electromagnetic performance of SYRFDR-PMSM. It can provide assistance for the initial design and optimization of SYRFDR-PMSM.

Given the ever-growing air travel industry, there is an increasing strain on the systems that provide safe flights. Different methods have to be adopted to help to cope with the increasing demand, especially in Southeast Asia. The purpose of this study is to sectorise one existing airspace to better manage sector workloads.

Cambodia’s airspace was chosen for this study because it had only one sector and it was quickly approaching its limit. In this paper, after characterising the airspace, it was first bi-partitioned using the spectral clustering algorithm. The weights of the resulting subgraphs were then balanced through a weight-balancing algorithm. Also, a post-processing algorithm established the sector boundary to be drawn. The method was first carried out on one test airspace. Following the successful sectorisation of the test airspace, the actual Cambodian airspace was sectorised. The resulting two new sectors were then calculated to be able to last for approximately five years before they would reach their capacity. Hence, a further sectorisation was carried out. This resulted in four sectors, which were projected to last more than 10 years.

The method produced satisfactory results. The methodology presented is proven to be effective in achieving the sectorisation. The workloads of the new sectors obtained are balanced, and the sector boundaries are at least 15 km away from the air routes and nodes. The methodology is also general and can be applied to different scenarios. This means that applications to other airspace in the region are possible, which can further help to increase the safety, efficiency and capacity of the air traffic movement in this region.

This paper presents one of the approaches for airspace sector designs. The problems are clearly presented with references. The authors discuss the advantages and disadvantages of subdividing airspace and the need to sectorise Cambodia’s airspace, and present a method to solve the sectorisation problem. It is very precious to apply methodologies and algorithms to real cases. The presented method offers significant advantages such as the ease of implementation and efficiency. The problems can easily be solved using standard linear algebra algorithms. Instead of looking at the airspace as a whole, and generating new sector boundaries, our algorithm uses current sector boundaries and bisects them. Moreover, only sectors that require sectorisation would be affected. This algorithm has the advantage of maintaining the current sector boundaries to prevent radical changes to daily operations. The Voronoi diagram used in this work does not generate polygonal cells. It instead calculates the area based on pixels. The advantage of doing this is that it offers higher flexibility. Also, the sector boundary is generated based on straight lines calculated by joining the midpoints of links. This is simple and ensures that sections of the sector boundary are made up of straight, distinct lines. The authors also discuss the problems of the method and presented solutions to them.

This paper attempts to review recent advances in wire bonding using copper wire.

Dozens of journal and conference articles published recently are reviewed.

The problems/challenges such as wire open and short tail defects, poor bondability for stitch/wedge bonds, oxidation of Cu wire, strain‐hardening effects, and stiff wire on weak support structures are briefly analysed. The solutions to the problems and recent findings/developments in wire bonding using copper wire are discussed.

Because of page limitation of the paper, only a brief review is conducted. Further reading is needed for more details.

This paper attempts to provide introduction to recent developments and the trends in wire bonding using copper wire. With the references provided, readers may explore more deeply by reading the original articles.

The purpose of this paper is to review recent advances in fine and ultra‐fine pitch wire bonding.

Dozens of journal and conference articles published recently are reviewed.

The problems/challenges such as possible wire sweep and decreased bonding strength due to small wire sizes, non‐sticking, metal pad peeling, narrow process windows, wire open and short tail defects are analysed. The solutions to the problems and recent findings/developments in fine and ultra‐fine pitch wire bonding are discussed.

Because of the page limitation, only brief discussions are given in this paper. Further reading is needed for more details.

This paper attempts to provide an introduction to recent developments and the trends in fine and ultra‐fine pitch wire bonding. With the references provided, readers may explore more deeply by reading the original articles.

This paper reports on thermal strain analysis of integrated circuit (IC) packages using the optical, atomic force microscope (AFM), and scanning electron microscope (SEM) Moiré methods. The advantages and disadvantages of a full field optical Moiré, a micro‐optical Moiré, AFM Moiré, and SEM Moiré methods are compared. The full field Moiré interferometry is used to investigate the deformations and strains induced by thermal loading in various packages at the macrolevel. The micro Moiré interferometry is used to study the strains in the small solder joints. An optical Moiré interferometer with a mini thermal‐cycling chamber can be used for real time measurements of thermal deformations and strains of IC packages under thermal testing. Furthermore, the novel methods, AFM Moiré and SEM Moiré, can be also utilized to measure thermally induced deformations and strains of IC packages conveniently using the equipment that is commonly and primarily used for many other applications.

The purpose of this paper is to review recent advances in wire bonding of low‐k devices.

Dozens of journal and conference articles published in 2005‐2008 are reviewed.

The paper finds that many articles have discussed and analysed problems/challenges such as bond pad metal peeling/lift, non‐sticking on pad, decreased bonding strength and lower wire‐bond assembly yield. The paper discusses the articles' solutions to the problems and recent findings/developments in wire bonding of low‐k devices.

Because of the page limitation, only brief discussions are given in this paper. Further reading is needed for more details.

The paper attempts to provide an introduction to recent developments and the trends in wire bonding of low‐k devices. With the references provided, readers may explore more deeply by reading the original articles.

This paper seeks to review recent advances in wire bonding, flip chip and lead‐free solder for advanced microelectronics packaging.

Of the 91 journal papers, 59 were published in 2005‐2007 and topics related to wire bonding, flip chip and lead‐free solder for advanced microelectronics packaging are reviewed.

Research on advanced wire bonding is continuously performed for advanced and complex applications such as stacked‐dies wire bonding, wire bonding of low‐k ultra‐fine‐pitch devices, and copper wire bonding. Owing to its many advantages, flip chip using adhesive has gained more popularity. Research on the reliability of lead‐free solder joints is being conducted world‐wide. The new challenges, solutions and new developments are discussed in this paper.

Because of page limitation of this review paper and the large number of the journal papers available, only a brief review is conducted. Further reading is needed for more details.

This review paper attempts to provide introduction to recent developments and the trends in terms of the topics for advanced microelectronics packaging. With the references provided, readers may explore more deeply, focusing on a particular issue.

This paper attempts to review recent advances in wire bonding using insulated wire and new challenges in wire bonding for advanced microelectronics packaging.

Dozens of journal articles, conference articles and patents published or issued in 2004‐2007 are reviewed.

The advantages and problems/challenges related to wire bonding using insulated wire are briefly analysed, and several solutions to the problems and recent findings/developments related to wire bonding using insulated wire are discussed.

Because of page limitation of the paper, only brief review is conducted. Further reading is needed for more details.

This paper attempts to provide introduction to recent developments and the trends in wire bonding using insulated wire. With the references provided, readers may explore more deeply by reading the original articles and patent documents.

The fan-out wafer level package (FOWLP) becomes more and more attractive and popular because of its flexibility to integrate diverse devices into a very small form factor. The strength of ultrathin FOWLP is low, and the low package strength often leads to crack issues. This paper aims to study the strength of thin FOWLP because the low package strength may lead to the reliability issue of package crack.

This paper uses the experimental method (three-point bending test) and finite element method (ANSYS simulation software) to evaluate the FOWLP strength. Two theoretical models of FOWLP strength are proposed. These two models are based on the location of FOWLP initial fracture point.

The results show that the backside protection tape does not have the ability to enhance the FOWLP strength, and the strength of over-molded structure FOWLP is superior to that of other structure FOWLPs with the same thickness level.

There is ample research about the silicon strength and silicon die strength. However, there is little research about the package level strength and no research about the FOWLP strength. The FOWLP is made up of various materials. The effect of individual component and external environment on the FOWLP strength is uncertain. Therefore, the study of strength behavior of FOWLP is significant.

This paper aims to review recent advances and applications of abrasive processes for microelectronics fabrications.

More than 80 patents and journal and conference articles published recently are reviewed. The topics covered are chemical mechanical polishing (CMP) for semiconductor devices, key/additional process conditions for CMP, and polishing and grinding for microelectronics fabrications and fan-out wafer level packages (FOWLPs).

Many reviewed articles reported advanced CMP for semiconductor device fabrications and innovative research studies on CMP slurry and abrasives. The surface finish, sub-surface damage and the strength of wafers are important issues. The defects on wafer surfaces induced by grinding/polishing would affect the stability of diced ultra-thin chips. Fracture strengths of wafers are dependent on the damage structure induced during dicing or grinding. Different thinning processes can reduce or enhance the fracture strength of wafers. In the FOWLP technology, grinding or CMP is conducted at several key steps. Challenges come from back-grinding and the wafer warpage. As the Si chips of the over-molded FOWLPs are very thin, wafer grinding becomes critical. The strength of the FOWLPs is significantly affected by grinding.

This paper attempts to provide an introduction to recent developments and the trends in abrasive processes for microelectronics manufacturing. With the references provided, readers may explore more deeply by reading the original articles. Original suggestions for future research work are also provided.