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Article
Publication date: 9 August 2021

Premmilaah Gunasegaran, Jagadheswaran Rajendran, Selvakumar Mariappan, Yusman Mohd Yusof, Zulfiqar Ali Abdul Aziz and Narendra Kumar

The purpose of this paper is to introduce a new linearization technique known as the passive linearizer technique which does not affect the power added efficiency (PAE) while…

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Abstract

Purpose

The purpose of this paper is to introduce a new linearization technique known as the passive linearizer technique which does not affect the power added efficiency (PAE) while maintaining a power gain of more than 20 dB for complementary metal oxide semiconductor (CMOS) power amplifier (PA).

Design/methodology/approach

The linearization mechanism is executed with an aid of a passive linearizer implemented at the gate of the main amplifier to minimize the effect of Cgs capacitance through the generation of opposite phase response at the main amplifier. The inductor-less output matching network presents an almost lossless output matching network which contributes to high gain, PAE and output power. The linearity performance is improved without the penalty of power consumption, power gain and stability.

Findings

With this topology, the PA delivers more than 20 dB gain for the Bluetooth Low Energy (BLE) Band from 2.4 GHz to 2.5 GHz with a supply headroom of 1.8 V. At the center frequency of 2.45 GHz, the PA exhibits a gain of 23.3 dB with corresponding peak PAE of 40.11% at a maximum output power of 14.3 dBm. At a maximum linear output power of 12.7 dBm, a PAE of 37.3% has been achieved with a peak third order intermodulation product of 28.04 dBm with a power consumption of 50.58 mW. This corresponds to ACLR of – 20 dBc, thus qualifying the PA to operate for BLE operation.

Practical implications

The proposed technique is able to boost up the efficiency and output power, as well as linearize the PA closer to 1 dB compression point. This reduces the trade-off between linear output power and PAE in CMOS PA design.

Originality/value

The proposed CMOS PA can be integrated comfortably to a BLE transmitter, allowing it to reduce the transceiver’s overall power consumption.

Details

Microelectronics International, vol. 38 no. 2
Type: Research Article
ISSN: 1356-5362

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Article
Publication date: 22 February 2021

Selvakumar Mariappan, Jagadheswaran Rajendran, Norlaili Mohd Noh, Yusman Yusof and Narendra Kumar

The purpose of this paper is to implement a highly linear 180 nm complementary metal oxide semiconductor (CMOS) power amplifier (PA) to meet the stringent linearity requirement of…

242

Abstract

Purpose

The purpose of this paper is to implement a highly linear 180 nm complementary metal oxide semiconductor (CMOS) power amplifier (PA) to meet the stringent linearity requirement of an long term evolution (LTE) signal with minimum trade-off to power added efficiency (PAE).

Design/methodology/approach

The CMOS PA is designed in a cascaded dual-stage configuration comprises a driver amplifier and a main PA. The gate voltage (VGS) of the driver amplifier is tuned to optimize its positive third-order transconductance (gm3) to be canceled with the main PA’s fixed negative gm3. The gm3 cancellation between these stages mitigates the third-order intermodulation product (IMD3) that contributes to enhanced linearity.

Findings

For driver’s VGS of 0.82 V with continuous wave signal, the proposed PA achieved a power gain of 14.5 dB with a peak PAE of 31.8% and a saturated output power of 23.3 dBm at 2.45 GHz. A maximum third-order output intercept point of 34 dBm is achieved at 20.2 dBm output power with a corresponding IMD3 of −33.4 dBc. When tested with a 20 MHz LTE signal, the PA delivers 19 dBm maximum linear output power for an adjacent channel leakage ratio specification of −30 dBc.

Originality/value

In this study, a novel cascaded gm3 cancellation technique has been implemented to achieve a maximum linear output power under modulated signals.

Details

Circuit World, vol. 48 no. 2
Type: Research Article
ISSN: 0305-6120

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Article
Publication date: 29 April 2014

Siti Maisurah Mohd Hassan, Yusman M. Yusof, Arjuna Marzuki, Nazif Emran Farid, Siti Amalina Enche Ab Rahim and Mohd Hafis M. Ali

The purpose of this paper is to present the high-frequency performance of 0.13-μm n-type metal-oxide-semiconductor (NMOS) transistors with various multi-finger configurations for…

187

Abstract

Purpose

The purpose of this paper is to present the high-frequency performance of 0.13-μm n-type metal-oxide-semiconductor (NMOS) transistors with various multi-finger configurations for implementation in millimeter-wave (mm-wave) frequency.

Design/methodology/approach

A folded-like double-gate transistor layout is designed to enable the transistor to work in the mm-wave region. Different sizes of transistors with variation in finger width (WF) and number of fingers (NF) were fabricated to determine the optimum size of the transistor. The extrinsic parasitic elements of selected transistors were extracted and investigated. The radio frequency (RF) performance of these samples were then analyzed and compared.

Findings

The proposed layout performed well with the highest maximum oscillation frequency (fmax) achieved at 122 GHz. Based on the comparison done, the optimum WF obtained for the layout is at 2.0 μm. It is found that the extrinsic parasitic capacitance is more dominant than the parasitic resistance in affecting the fmax. In s-parameter analysis, it is observed that the transistor with the least NF has smaller variance in small-signal gain throughout the measurement frequency. The maximum stable gain for the samples is also found to be roughly similar and independent of NF.

Originality/value

A new layout structure for an NMOS transistor that works in mm-wave frequency is proposed. Experimental analyses presented here cover for both NF and WF, unlike others which focus on either NF or WF only.

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