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To simulate large parasitic resistive networks, one must reduce the size of the circuit models through methods that are accurate and preserve terminal connectivity and network sparsity. The purpose here is to present such a method, which exploits concepts from graph theory in a systematic fashion.

The model order reduction problem is formulated for parasitic resistive networks through graph theory concepts and algorithms are presented based on the notion of vertex cut in order to reduce the size of electronic circuit models. Four variants of the basic method are proposed and their respective merits discussed.

The algorithms proposed enable the production of networks that are significantly smaller than those produced by earlier methods, in particular the method described in the report by Lenaers entitled “Model order reduction for large resistive networks”. The reduction in the number of resistors achieved through the algorithms is even more pronounced in the case of large networks.

The paper seems to be the first to make a systematic use of vertex cuts in order to reduce a parasitic resistive network.

The main aim of this study is the modelling of the interaction of on‐chip components with their electromagnetic environment.

The integrated circuit is decomposed in passive and active components interconnected by means of terminals and connectors which represent intentional and parasitic couplings of a capacitive and inductive nature. Reduced order models are extracted independently for each component.

The paper shows that one of the main theoretical problems encountered in the modelling of RF components is the difficulty to define a unique terminal voltage, independent of the integration path (this independence being a condition to allow the connection of the component in an electric circuit, where the voltage does not depend of the path shape). The concept of an electromagnetic circuit element that allows the interconnection between IC models is proposed as a solution for this drawback. The system is described either with EM field models, or by electric/magnetic circuits. By using the new concept of hooks, the EM interaction is described effectively with a reduced number of quantities.

Since hooks have a virtual character, their identification is the result of an optimization procedure. By increasing their number the model accuracy is improved as also is the computational effort. The optimal automatic identification of electric and magnetic hooks is the subject of further research. Currently, the hooks are placed manually.

The modelling of IC components with hooks is part of a new methodology that takes a layout description of typical RF functional blocks that will operate at RF frequencies up to 60 GHz and transform them into sufficiently accurate, reliable electrical simulation models, taking EM coupling and variability into account. This will decrease extra design iterations, over‐dimensioning or complete failures in the design cycle of RF‐IC.

For the first time, the concept of magnetic terminals is used to describe interactions in RF integrated circuits. These EM “hooks” are defined in mathematical terms, as proper boundary conditions. The concept of hooks is also new. The proposed modeling methodology for EM coupling is also new. The paper is useful for nEDA designers.

Imperfections in manufacturing processes may cause unwanted connections (faults) that are added to the nominal, “golden”, design of an electronic circuit. By fault simulation one simulates all situations. Normally this leads to a large list of simulations in which for each defect a steady-state (direct current (DC)) solution is determined followed by a transient simulation. The purpose of this paper is to improve the robustness and the efficiency of these simulations.

Determining the DC solution can be very hard. For this the authors present an adaptive time-domain source stepping procedure that can deal with controlled sources. The method can easily be combined with existing pseudo-transient procedures. The method is robust and efficient. In the subsequent transient simulation the solution of a fault is compared to a golden, fault-free, solution. A strategy is developed to efficiently simulate the faulty solutions until their moment of detection.

The paper fully exploits the hierarchical structure of the circuit in the simulation process to bypass parts of the circuit that appear to be unaffected by the fault. Accurate prediction and efficient solution procedures lead to fast fault simulation.

The fast fault simulation helps to store a database with detectable deviations for each fault. If such a detectable output “matches” a result of a product that has been returned because of malfunctioning it helps to identify the subcircuit that may contain the real fault. One aims to detect as much as possible candidate faults. Because of the many options the simulations must be very efficient.