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This paper attempted a novel approach for system-level modeling and simulation of sigma-delta modulator for low-frequency CMOS integrated analog to digital interfaces. Comparative analysis of various architectures topologies, circuit implementation techniques are described with analytical procedure for effective selection of topologies for targeted specifications.

Virtual instruments are presented in labview environment to analyze the correlation of circuit-level non-ideal effects with key design parameters over sampling ratio, coarse quantizer bits and loop filter order. A fourth-order single-loop sigma-delta modulator is designed and verified in MATLAB simulink environment with careful selection of integrator weights to meet stable desired performance.

The proposed designed achieved SNDR of 122 dB and 20 bit resolution satisfying high-resolution requirements of low-frequency biomedical signal processing applications. Even though the simulation performed at behavioral level, the results obtained are considered as accurate, by including all non-ideal and non-linear circuit errors in simulation process.

Virtual instruments using labview environment used to analyze the correlation of circuit-level non-ideal effects with key design parameters over sampling ratio, coarse quantizer bits and loop filter order for accurate design.

A third-order discrete time sigma delta modulator (SDM) is proposed with optimum performance by addressing instability and power dissipations issues, and a novel SDM architecture is designed and verified in behavioural modelling in MATLAB/SIMULINK environment. Simulation results show that performance parameters of proposed modulator achieved SNR of 105.41 dB, SNDR of 101.96 dB and DR of 17 bits for the signal bandwidth of 20 kHz.

This paper describes single-loop SDM design with optimum selection of integrator weights for physiological signal processing in IoT applications.

The proposed discrete time modulator designed with 1-bit quantizer and optimum oversampling ratio proved as power efficient. Integrator scaling coefficients are generated in LabVIEW environment for pure third-order noise shaping.

This paper contains the novelty in the work, and it is suitable for cognitive Internet of Things applications.