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Article
Publication date: 1 February 2018

Mohammad Gharaibeh

This paper aims to present a reliability performance assessment of electronic packages subjected to harmonic vibration loadings by using a statistical factorial analysis…

230

Abstract

Purpose

This paper aims to present a reliability performance assessment of electronic packages subjected to harmonic vibration loadings by using a statistical factorial analysis technique. The effects of various geometric parameters, the size and thickness of the printed circuit board and component and solder interconnect dimensions on the fundamental resonant frequency of the assembly and the axial strain of the most critical solder joint were thoroughly investigated.

Design/methodology/approach

A previously published analytical solution for the problem of electronic assembly vibration was adopted. This solution was modified and used to generate the natural frequency and solder axial strains data for various package geometries. Statistical factorial analysis was used to analyze these data.

Findings

The results of the present study showed that the reliability of electronic packages under vibration could be significantly enhanced by selecting larger and thicker printed circuit boards and thinner and smaller electrical components. Additionally, taller and thinner solders might also produce better reliability behavior.

Originality/value

The results of this investigation can be very useful in the design process of electronic products in mechanical vibration environments.

Details

Soldering & Surface Mount Technology, vol. 30 no. 3
Type: Research Article
ISSN: 0954-0911

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Article
Publication date: 31 July 2007

Z.W. Zhong, T.Y. Tee and J‐E. Luan

This paper seeks to review recent advances in wire bonding, flip chip and lead‐free solder for advanced microelectronics packaging.

1878

Abstract

Purpose

This paper seeks to review recent advances in wire bonding, flip chip and lead‐free solder for advanced microelectronics packaging.

Design/methodology/approach

Of the 91 journal papers, 59 were published in 2005‐2007 and topics related to wire bonding, flip chip and lead‐free solder for advanced microelectronics packaging are reviewed.

Findings

Research on advanced wire bonding is continuously performed for advanced and complex applications such as stacked‐dies wire bonding, wire bonding of low‐k ultra‐fine‐pitch devices, and copper wire bonding. Owing to its many advantages, flip chip using adhesive has gained more popularity. Research on the reliability of lead‐free solder joints is being conducted world‐wide. The new challenges, solutions and new developments are discussed in this paper.

Research limitations/implications

Because of page limitation of this review paper and the large number of the journal papers available, only a brief review is conducted. Further reading is needed for more details.

Originality/value

This review paper attempts to provide introduction to recent developments and the trends in terms of the topics for advanced microelectronics packaging. With the references provided, readers may explore more deeply, focusing on a particular issue.

Details

Microelectronics International, vol. 24 no. 3
Type: Research Article
ISSN: 1356-5362

Keywords

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Article
Publication date: 26 August 2021

Elwin Heng and Mohd Zulkifly Abdullah

This paper focuses on the fluid-structure interaction (FSI) analysis of moisture induced stress for the flip chip ball grid array (FCBGA) package with hydrophobic and hydrophilic…

173

Abstract

Purpose

This paper focuses on the fluid-structure interaction (FSI) analysis of moisture induced stress for the flip chip ball grid array (FCBGA) package with hydrophobic and hydrophilic materials during the reflow soldering process. The purpose of this paper is to analyze the influence of moisture concentration and FCBGA with hydrophobic material on induced pressure and stress in the package at varies times.

Design/methodology/approach

The present study analyzed the warpage deformation during the reflow process via visual inspection machine (complied to Joint Electron Device Engineering Council standard) and FSI simulation by using ANSYS/FLUENT package. The direct concentration approach is used to model moisture diffusion and ANSYS is used to predict the Von-Misses stress. Models of Test Vehicle 1 (similar to Xie et al., 2009b) and Test Vehicle 2 (FCBGA package) with the combination of hydrophobic and hydrophilic materials are performed. The simulation for different moisture concentrations with reflows process time has been conducted.

Findings

The results from the mechanical reliability study indicate that the FSI analysis is found to be in good agreement with the published study and acceptable agreement with the experimental result. The maximum Von-Misses stress induced by the moisture significantly increased on FCBGA with hydrophobic material compared to FCBGA with a hydrophilic material. The presence of hydrophobic material that hinders the moisture desorption process. The analysis also illustrated the moisture could very possibly reside in electronic packaging and developed beyond saturated vapor into superheated vapor or compressed liquid, which exposed electronic packaging to higher stresses.

Practical implications

The findings provide valuable guidelines and references to engineers and packaging designers during the reflow soldering process in the microelectronics industry.

Originality/value

Studies on the influence of moisture concentration and hydrophobic material are still limited and studies on FCBGA package warpage under reflow process involving the effect of hydrophobic and hydrophilic materials are rarely reported. Thus, this study is important to effectively bridge the research gap and yield appropriate guidelines in the microelectronics industry.

Details

Soldering & Surface Mount Technology, vol. 34 no. 2
Type: Research Article
ISSN: 0954-0911

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Article
Publication date: 8 May 2009

Z.W. Zhong

The purpose of this paper is to review recent advances in fine and ultra‐fine pitch wire bonding.

635

Abstract

Purpose

The purpose of this paper is to review recent advances in fine and ultra‐fine pitch wire bonding.

Design/methodology/approach

Dozens of journal and conference articles published recently are reviewed.

Findings

The problems/challenges such as possible wire sweep and decreased bonding strength due to small wire sizes, non‐sticking, metal pad peeling, narrow process windows, wire open and short tail defects are analysed. The solutions to the problems and recent findings/developments in fine and ultra‐fine pitch wire bonding are discussed.

Research limitations/implications

Because of the page limitation, only brief discussions are given in this paper. Further reading is needed for more details.

Originality/value

This paper attempts to provide an introduction to recent developments and the trends in fine and ultra‐fine pitch wire bonding. With the references provided, readers may explore more deeply by reading the original articles.

Details

Microelectronics International, vol. 26 no. 2
Type: Research Article
ISSN: 1356-5362

Keywords

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Article
Publication date: 23 January 2009

Z.W. Zhong

This paper attempts to review recent advances in wire bonding using copper wire.

2210

Abstract

Purpose

This paper attempts to review recent advances in wire bonding using copper wire.

Design/methodology/approach

Dozens of journal and conference articles published recently are reviewed.

Findings

The problems/challenges such as wire open and short tail defects, poor bondability for stitch/wedge bonds, oxidation of Cu wire, strain‐hardening effects, and stiff wire on weak support structures are briefly analysed. The solutions to the problems and recent findings/developments in wire bonding using copper wire are discussed.

Research limitations/implications

Because of page limitation of the paper, only a brief review is conducted. Further reading is needed for more details.

Originality/value

This paper attempts to provide introduction to recent developments and the trends in wire bonding using copper wire. With the references provided, readers may explore more deeply by reading the original articles.

Details

Microelectronics International, vol. 26 no. 1
Type: Research Article
ISSN: 1356-5362

Keywords

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Article
Publication date: 13 April 2010

Mei-Ling Wu

The purpose of this paper is to identify the critical parameters that influence ball grid array and chip size package fatigue life in a random vibration environment by using a…

314

Abstract

Purpose

The purpose of this paper is to identify the critical parameters that influence ball grid array and chip size package fatigue life in a random vibration environment by using a design of experimental (DOE) approach using simulation results.

Design/methodology/approach

The use of DOE and analysis of variation to identify the critical parameters and a response surface to generate a functional form for global modeling would be determined. Once the global modeling’s functional form was known, it can be used as boundary condition, which would be input to a local model. Knowing the critical stress, one would estimate the fatigue life from a damage model. It is the curvature of the printed wiring board in the region of the component of interest that is driving the component’s solder joint damage. The approach in this present work involves global-local modeling approaches. In the global model approach, the vibration response of the printed circuit board (PCB) will be determined.

Findings

This global model will give the response of the PCB at specific component locations of interest. This response is then fed into a local stress analysis for accurate assessment of the critical stresses in the solder joints of interest. The stresses are then fed into a fatigue damage model to predict the life.

Originality/value

The analysis proposed in this paper uses a failure type approach to damage analysis and involves global and local model approaches.

Details

Soldering & Surface Mount Technology, vol. 22 no. 2
Type: Research Article
ISSN: 0954-0911

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Article
Publication date: 22 November 2018

Mohammad Gharaibeh, Aaron J. Stewart, Quang T. Su and James M. Pitarresi

This paper aims to investigate and compare the reliability performance of land grid array (LGA) and ball grid array (BGA) solders, as well as the SAC105 and 63Sn37Pb solder…

187

Abstract

Purpose

This paper aims to investigate and compare the reliability performance of land grid array (LGA) and ball grid array (BGA) solders, as well as the SAC105 and 63Sn37Pb solder alloys, in vibration loading conditions.

Design/methodology/approach

Reliability tests were conducted using a sine dwell with resonance tracking vibration experiment. Finite element simulations were performed to help in understanding the observed failure trends.

Findings

Reliability results showed that the tin-lead solders out-perform lead-free solders in vibrations loading. Additionally, the LGA solder type could provide a better vibration reliability performance than BGA solders. Failure analysis results showed that in LGAs, the crack is initiated at the printed circuit board side and at the component side in BGAs. In both types, the crack is propagated throughout in the intermetallic compound layer.

Originality/value

In literature, there is a lack of published data in the comparison between LGA and BGA reliability performance in vibration loadings. This paper provides useful insights in the vibration reliability behavior of the two common solder joint types.

Details

Soldering & Surface Mount Technology, vol. 31 no. 2
Type: Research Article
ISSN: 0954-0911

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Article
Publication date: 3 February 2012

De‐Shin Liu, Chang‐Lin Hsu, Chia‐Yuan Kuo, Ya‐Ling Huang, Kwang‐Lung Lin and Geng‐Shin Shen

The purpose of this paper is to present a novel high speed impact testing method for evaluating the effects of low temperatures on eutectic and lead‐free solder joints…

593

Abstract

Purpose

The purpose of this paper is to present a novel high speed impact testing method for evaluating the effects of low temperatures on eutectic and lead‐free solder joints. Interfacial cracking failure of Sn‐based and Pb‐free solders at subzero temperatures is of significant concern for electronic assemblies that operate in harsh environments.

Design/methodology/approach

This paper presents a newly designed low temperature control system coupled with an Instron micro‐impact testing machine, which offers a package level test for solder bumps, and that is used at subzero temperature ranges as low as −40°C. This study examined the failure characteristics of 63Sn‐37Pb (Sn37Pb) and 96.5Sn‐3Ag‐0.5Cu (SAC305) solder joints at temperatures ranging from room temperature (R.T.) to −40°C, and at impact speeds of 1 m/s.

Findings

Three types of failure mode were identified: M1 interfacial fracture with no residual solder remaining on the pad (interfacial cracking); M2 interfacial fracture with residual solder persisting on the pad (mixed mode failure); and M3 solder ball fracture (bulk solder cracking). The experimental results indicated that the energy to peak load for both types of solders decreased significantly, by approximately 35 percent to 38 percent when the test temperature was reduced from R.T. to −40°C. In addition, the peak load of the Sn37Pb solder joint increased noticeably with a decreasing test temperature. However, the peak load of the SAC305 specimen remained virtually unchanged with a reduction in the temperature. The Sn37Pb solder joints failed in an M3 failure mode under all the considered testing temperatures. The SAC305 solder joints displayed both M1 and M2 failure modes at R.T.; however, they failed almost exclusively in M1 mode at the lowest test temperature of −40°C.

Originality/value

This paper presents a novel technique for evaluating high‐speed impact strength and energy absorbance of Sn‐based and Pb‐free solders at the chip level within a low temperature control system. To overcome the drawbacks experienced in other studies, this study focused specifically on cryo‐impact testing systems and the performed experimental steps to improve the accuracy of post‐test analysis.

Details

Soldering & Surface Mount Technology, vol. 24 no. 1
Type: Research Article
ISSN: 0954-0911

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Article
Publication date: 27 May 2014

Weisheng Xia, Ming Xiao, Yihao Chen, Fengshun Wu, Zhe Liu and Hongzhi Fu

– The purpose of this paper is to study the thermal warpage of a plastic ball grid array (PBGA) mounted on a printed circuit board (PCB) during the reflow process.

664

Abstract

Purpose

The purpose of this paper is to study the thermal warpage of a plastic ball grid array (PBGA) mounted on a printed circuit board (PCB) during the reflow process.

Design/methodology/approach

A thermal-mechanical coupling method that used finite-element method software (ANSYS 13.1) was performed. Meanwhile, a shadow moiré apparatus (TherMoiré PS200) combined with a heating platform was used for the experimental measurement of the warpage of PBGA according to the JEDEC Standard.

Findings

The authors found that the temperature profiles taken from the simulated results and experimental measurement are consistent with each other, only with a little and acceptable difference in the maximum temperatures. Furthermore, the maximum warpage measurements during the reflow process are 0.157 mm and 0.149 mm for simulation and experimental measurements, respectively, with a small 5.37 per cent difference. The experimental measurement and simulated results are well correlated. Based on the validated finite element model, two factors, namely, the thickness and dimension of PCB, are explored about their effect on the thermal warpage of PBGA mounted on PCB during the reflow process.

Practical implications

The paper provides a thorough parametrical study of the thermal warpage of PBGA mounted on PCB during the reflow process.

Originality/value

The findings in this paper illustrate methods of warpage study by combination of thermal-mechanical finite element simulation and experimental measurement, which can provide good guidelines of the PCB design in the perspective of thermal warpage during the reflow process.

Details

Soldering & Surface Mount Technology, vol. 26 no. 3
Type: Research Article
ISSN: 0954-0911

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Article
Publication date: 20 February 2023

Soufyane Belhenini, Imad El Fatmi, Caroline Richard and Abdellah Tougui

This study aims to contribute to the numerical modelling of drop impact on a flip-chip component assembled on printed circuit boards using solder micro-bumps. This contribution is…

68

Abstract

Purpose

This study aims to contribute to the numerical modelling of drop impact on a flip-chip component assembled on printed circuit boards using solder micro-bumps. This contribution is based on the introduction of non-linear fracture mechanics in the numerical approach.

Design/methodology/approach

The integration of non-linear fracture mechanics into the numerical approach requires the proposal and validation of several simplifying assumptions. Initially, a dynamic 3D model was simplified to a dynamic 2D model. Subsequently, the dynamic 2D model is replaced with an equivalent static 2D model. The equivalent static 2D model was used to perform calculations considering the non-linear fracture mechanics. A crack was modelled in the critical bump. The J-integral was used as a comparative parameter to study the effects of crack length, crack position and chip thickness on the fracture toughness of the solder bump.

Findings

The different simplifying assumptions were validated by comparing the results obtained by the various models. Numerical results showed a high risk of failure at the critical solder bump in a zone close to the intermetallic layer. The obtained results were in agreement with the post-test observations using the “Dye and Pry” methods.

Originality/value

The originality of this study lies in the introduction of non-linear fracture mechanics to model the mechanical response of solder bumps during drop impact. This study led to some interesting conclusions, highlighting the advantage of introducing non-linear fracture mechanics into the numerical simulations of microelectronic components during a drop impact.

Details

Soldering & Surface Mount Technology, vol. 35 no. 4
Type: Research Article
ISSN: 0954-0911

Keywords

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