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In this chapter, the author considers a three-sector general equilibrium model in the context of a developing nation to find out the impact of an increase in foreign capital inflow on the welfare level of the nation. Comparative static analysis reveals that an increase in the inflow of foreign capital causes redistribution across the factors of production and a reallocation of resources, reflected through the change in output. Moreover, the author considers the case of technology transfer and proves that an increase in foreign capital inflow makes the country better off in terms of social welfare even if the foreign capital is fully repatriated. Hence, this work shows that in the absence of any trade distortion, a partial investment liberalisation causes a welfare gain for a small open economy.

This paper aims to propose a new lector-based domino and examine it with inputs and clock signal combination in a 45-nm dual-threshold footerless domino circuit for reduced leakage current.

In this technique, p-type and n-type leakage control transistors (LCTs) are introduced between pull-up and pull-down networks, and the gate of one is controlled by the source of the other. A high-threshold transistor is used in the input for reducing gate oxide leakage current, which becomes dominant in nanometre technology. Simulations were based on a 45-nm BISM 4 model using an HSPICE simulator for proposed domino circuits.

The result shows that CHIL (clock high and input low) state is ineffective for lowering leakage current and the conventional CHIH (clock high and input high) state is only effective to suppress the leakage at low temperature for wide fan-in domino circuits. At high temperature, CLIL (clock low and input low) state is preferable to reduce the leakage current for low fan-in domino, but for high fan-in domino, CHIH state is preferred. The proposed circuit technique for AND2, OR2, OR4 and OR8 circuits reduces the active power consumption by 50.94 to 75.68 per cent and by 64.85 to 86.57 per cent at low and high die temperatures, respectively, when compared to the standard dual-threshold voltage domino logic circuits.

The research proposes a new leakage reduction technique used in domino circuits and also evaluates the state for leakage reduction which can be used for low-power dynamic circuits.

This paper aims to propose a new sleep signal controlled footless domino circuit for reducing the subthreshold and gate oxide leakage currents.

In the proposed circuit, a P channel MOSFET (PMOS) sleep switch transistor is inserted between the power supply and the output node. The sleep transistor, the source of the pull-down network, and the source of the N channel MOSFET (NMOS) transistor of the output inverter are controlled by this additional sleep signal to place the footless domino circuit in a low leakage state.

The authors simulate the proposed circuit by using HSPICE in 45-nm CMOS technology for OR and AND logic gates such as OR2, OR4, OR8, AND2 and AND4 at 25°C and 110°C. The proposed circuit reduces leakage power consumption as compared to the existing circuits.

The proposed circuit significantly reduces the total leakage power consumption up to 99.41 and 99.51 per cent as compared to the standard dual-threshold voltage footless domino circuits at 25°C and 110°C, respectively, and up to 93.79 and 97.98 per cent as compared to the sleep control techniques at 25°C and 110°C, respectively. Similarly, the proposed circuit reduces the active power consumption up to 26.76 and 86.25 per cent as compared to the standard dual-threshold voltage and sleep control techniques footless domino circuits at 25°C and 110°C, respectively.

With the onset of globalization in developing economies, policymakers express serious concerns about the role of the informal economy, a concern also mirrored in the United Nations (UN) sustainable development goals (SDGs). Numerous attempts have been made to analyse the general equilibrium consequences of globalization in terms of foreign capital inflow on the informal sector in a developing economy. These studies examined the impact of foreign capital inflow through the channels of resource reallocation across sectors and adjustment in the factor and commodity prices. Nevertheless, the efficacy of these channels is contingent upon the assumption of perfectly competitive product markets that is pertinent in the majority of the studies. This chapter attempts to incorporate imperfect competition in the informal economy in a Heckscher–Ohlin-type multi-factor, multi-sector general equilibrium setup. We assume the existence of imperfection in both a homogeneous good-producing industry and a product-differentiating industry and examine how foreign capital inflow in the presence of imperfect competition affects the informal workers, industrial and firm output, product diversity, national income, and welfare. We also analyse how the consequences of foreign capital inflow on the informal economy can vary with the degree of product market imperfection. It is obtained that varying degrees of product market imperfection in the informal economy have only quantitative (magnitude) effects; however, qualitative (directional) effects remain unchanged.

This paper aims to propose a new fin field-effect transistor (FinFET)-based domino technique low-power series connected foot-driven transistors logic in 32 nm technology and examine its performance parameters by performing transient analysis.

In the proposed technique, the leakage current is reduced at footer node by a division of current to improve the performance of the circuit in terms of average power consumption, propagation delay and noise margin. Simulation of existing and proposed techniques are carried out in FinFET and complementary metal-oxide semiconductor technology at FinFET 32 nm technology for 2-, 4-, 8- and 16-input domino OR gates on a supply voltage of 0.9 V using HSPICE.

The proposed technique shows maximum power reduction of 77.74% in FinFET short gate (SG) mode in comparison with current-mirror-based process variation tolerant (CPVT) technique and maximum delay reduction of 51.34% in low power (LP) mode in comparison with CPVT technique at a frequency of 100 MHz. The unity noise gain of the proposed circuit is 1.10× to 1.54× higher in comparison with different existing techniques in FinFET SG mode and 1.11× to 1.71× higher in FinFET LP mode. The figure of merit of the proposed circuit is up to 15.77× higher in comparison with existing domino techniques.

The research proposes a new FinFET-based domino technique and shows improvement in power, delay, area and noise performance. The proposed design can be used for implementing high-speed digital circuits such as microprocessors and memories.

The purpose of this paper is to develop a generalized model of the nonlinear conductivity of varistor ceramic suitable for solving problems of prediction and control of ceramic nonlinearity, stability of varistor properties.

The modeling of current-voltage characteristic of the intergranular barrier in metal oxide varistor ceramics is based on the development of the algorithm. It includes all the known mechanisms of electrotransfer in a wide range of voltages and currents of the current-voltage characteristics, and also takes into account the deviation of the barrier form the Schottky barrier.

The models of double Schottky barrier and double barrier of arbitrary form, as well as the algorithms for calculating the current-voltage characteristics of a single intergranular potential barrier and a separate “microvaristor” with the use of the most well-established understanding of the main mechanisms of electrical are developed. The results of current-voltage characteristics modeling correspond to the existing understanding of the nonlinear electrical conductivity varistor ceramics are based on zinc oxide. The model of double barrier of arbitrary form takes into account the deviation of the barrier form the Schottky barrier which is important in predicting the deformation of the current-voltage characteristics of the varistor products in the process of degradation.

The relation between the form of the current-voltage characteristic and the distribution profile of the donor concentration in the surface regions of the semiconductor crystallites constituting the intergranular potential barrier is established. The accumulation of donors in the space charge region leads to the increase in the current on the prebreakdown region of the current-voltage characteristic and the reduction of voltage corresponding to the breakdown region beginning of the current-voltage characteristic. The significant role of the interlayer in the formation of current-voltage characteristic of the intergranular potential barrier is shown.

The purpose of this paper is to explore and develop specific models of the kinetics of isothermal depolarization currents (IDC) and the corresponding methods for the diagnostics of the physical parameters of localized electronic states (LES) in heterogeneous materials and corresponding polycrystalline semiconductor materials and heterogeneous insulators with a conductive phase.

Analysis of the kinetics of isothermal depolarization on the basis of the models allowed the authors to establish a sufficient level of their information content. This also allowed the possibility of applying for research and testing of heterogeneous structures of electronic technique.

Optimal conditions (full charge of LES on one side of the object and full discharge on the other side) and the correction factors, allowed the researchers to find concentration of these states using the developed models.

This paper uses a particular method to determine and test the parameters of LES, including operations of determining the time constant of IDC signal from its frequency spectrum, finding the ionization energy and the capture coefficient of electrons from the temperature dependence of this time constant, determining the concentration based on the integration of the time dependence of current density of IDC in the time interval that boundaries are determined from the limited range of frequencies of the signal IDC spectrum has been proposed, validated and verified by numerical experiments.

The present chapter throws light on the famous and very important issue of using eco-friendly, pollution free technology, named as ‘green technology’ or ‘green capital’ by developing economies in the sphere of environmental economics by using general equilibrium framework and tries to examine its impact on different polluting and non-polluting sectors of the economy. The present chapter has done so by using the concepts of ‘regime change’ and ‘endogenised green capital’ – these are the unique features of this work. Here, the authors have come across interesting outcomes by encompassing trade liberalisation in the form of international green capital immobility and international green capital mobility and it leads to an expansion of the sector that utilises it.

The two-tank level control system is one of the real-world's second-order system (SOS) widely used as the process control in industries. It is normally operated under the Proportional integral and derivative (PID) feedback control loop. The conventional PID controller performance degrades significantly in the existence of modeling uncertainty, faults and process disturbances. To overcome these limitations, the paper suggests an interval type-2 fuzzy logic based Tilt-Integral-Derivative Controller (IT2TID) which is modified structure of PID controller.

In this paper, an optimization IT2TID controller design for the conical, noninteracting level control system is presented. Regarding to modern optimization context, the flower pollination algorithm (FPA), among the most coherent population-based metaheuristic optimization techniques is applied to search for the appropriate IT2FTID's and IT2FPID's parameters. The proposed FPA-based IT2FTID/IT2FPID design framework is considered as the constrained optimization problem. System responses obtained by the IT2FTID controller designed by the FPA will be differentiated with those acquired by the IT2FPID controller also designed by the FPA.

As the results, it was found that the IT2FTID can provide the very satisfactory tracking and regulating responses of the conical two-tank noninteracting level control system superior as compared to IT2FPID significantly under the actuator and system component faults. Additionally, statistical Z-test carried out for both the controllers and an effectiveness of the proposed IT2FTID controller is proven as compared to IT2FPID and existing passive fault tolerant controller in recent literature.

Application of new metaheuristic algorithm to optimize interval type-2 fractional order TID controller for nonlinear level control system with two type of faults. Also, proposed method will compare with other method and statistical analysis will be presented.