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An integrated Web engine (IWE) has been developed by the Internetworking program at Dalhousie University, Halifax, Canada to deliver remote learning experience to geographically remote Master's students. The University intends to increase its student base through online education, retaining the same quality of interactions as the onsite program. To this end, the IWE accommodates three technology‐enabled learning environments that correlate with the three pedagogical approaches and types of onsite interaction. Discusses the e‐learning metrics, pedagogical and technical considerations that influence the design and implementation of the IWE environment. The IWE uses de facto networking standards, commercial and broadband Internet connectivity to ensure real‐time secure interaction with equipment and deliver lectures respectively. A four‐tier role architecture, consisting of faculty, local, remote facilitators, and students, has been determined to be appropriate and adapted to maintain academic integrity and offer the same quality of interaction as the onsite program.

Privacy and security of personal data is the prime concern in any communication. Security algorithms play a crucial role in privacy preserving and are used extensively. Therefore, these algorithms need to be effective as well as energy-efficient. Advanced Encryption Standards (AES) is one of the efficient security algorithms. The principal purpose of this research is to design Energy efficient implementation of AES, as it is one of the important aspects for a step toward green computing.

This paper presents a low voltage complementary metal oxide semiconductor (LVCMOS) based energy efficient architecture for AES encryption algorithm on Field Programmable Gate Array (FPGA) platform. The experiments are performed for five different FPGAs at different input/output standards of LVCMOS. Experiments are performed separately at two frequencies (default and 1.6 GHz).

The comparative study of total on-chip power consumption for different frequency suggested that LVCMOS12 performed best for all the FPGAs. Also, Kintex-7 Low Voltage was found to be the best performing FPGA. At 1.6 GHz frequency, the authors observed 55% less on-chip power consumption when switched from Artix-7 with LVCMOS33 (maximum power consuming combination) to Kintex-7 Low Voltage with LVCMOS12. Mathematical models are developed for the proposed design.

The green implementation of AES algorithm based on LVCMOS standards has not been explored yet by researchers. The energy efficient implementation of AES will certainly be beneficial for society as it will consume less power and dissipate lesser heat to environment.