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The purpose of this paper is to analyze the effect of driver size and number of shells on propagation delay and power for multi‐walled carbon nanotubes (MWCNT) interconnects at 22 nm technology node.

An equivalent circuit model of MWCNT is used for estimation and analysis of propagation delay and power. The delay and power through MWCNT and Cu interconnects are compared for various driver sizes and number of MWCNT shells.

The SPICE simulation results show that the MWCNT interconnect has lower propagation delay than Cu interconnects. The delay ratio of MWCNT to Cu decreases with increase in length for different driver size and number of MWCNT shells. However, the delay ratio increases with reduction in number of MWCNT shells. The ratio of average power consumption (MWCNT/Cu) also decreases with the variation in driver size and numbers of shells with respect to the length of interconnect. The theoretical study proves CNTs to be better alternatives against copper on the ground of performance parameters.

Several challenges remain to be overcome in the areas of fabrication and process integration for CNTs. Lowering of metal nanotube contact resistance would be vital, especially for local interconnect and via applications. Moreover, rigorous characterization and modeling of electromagnetic interactions in CNT bundles; 3‐D (metal) to 1‐D (CNT) contact resistance; impact of defects on electrical and thermal properties; and high‐frequency effects are being seen as additional challenges.

This paper investigates, assesses and compares the performance of carbon nanotubes (CNT) based interconnects as prospective alternatives to copper wire interconnects in future VLSI chips. Multi walled CNTs assure for long/global interconnect applications.

The aim of this paper is to analyze the effects of aggressor‐line load variations (both active gate and passive capacitive loads) on the non‐ideal effects of a coupled VLSI‐interconnect system.

Signal delay, power dissipation and crosstalk noise in interconnect can be influenced by variation in load of another interconnect which is coupled to it. For active gate and passive capacitive load variations, such effects are studied through SPICE simulations of a coupled interconnect pair in a 0.13 μm technology. Crosstalk between a coupled pair, is affected by transition time of the coupled signal, interconnect length, distance between interconnects, size of driver and receiver, pattern of input, direction of flow of signal and clock skew. In this work, influence of an aggressor‐line load variations (both active gate and passive capacitive loads) on the non‐ideal effects of delay, power consumption and crosstalk in a victim‐line of a coupled VLSI‐interconnect system are determined through SPICE simulation. In this experiment, the victim line is terminated by a fixed capacitive load and the coupled to aggressor line has variable load, either passive capacitive or active gate. Four different input signal cases have been considered for the two types of variable load. Distributed RLC transmission model of interconnect is considered for the SPICE simulations.

The simulation results reveal that the effects are much dependent on the type of load and signal variations at the inputs of the two mutually coupled interconnects. Load control at the aggressor far end can be used to minimize some of the adverse effects of crosstalk.

This paper shows that in interconnect, signal delay, power consumption and crosstalk are all affected by load variations in a coupled neighboring interconnect.

This paper aims to propose to study the control of tube parameters in terms of diameter, separation between adjacent tubes and length, on delay and power dissipation in single-walled carbon nanotube (SWCNT) bundle interconnect for VLSI circuits.

The paper considers a distributed-RLC model of interconnect. A CMOS-inverter driving a distributed-RLC model of interconnect with load of 1 pF. A 0.1 GHz pulse of 2 ns rise time provides input to the CMOS-inverter. For SPICE simulation, predictive technology model (PTM) is used for the CMOS-driver. The performance of this setup is studied by SPICE simulation in 22 nm technology node. The results are compared with those of currently used copper interconnect.

SPICE simulation results reveal that delay increases with increase in separation between tubes and diameter whereas the reverse is true for power dissipation. The authors also find that SWCNT bundle interconnects are of lower delay than copper interconnect at various lengths and higher power dissipation due to dominance of larger capacitance of tube bundle.

The investigations show that tube parameters can control delay and this can also be utilized to decrease power dissipation in SWCNT bundle interconnects for VLSI applications.

To analyze factors affecting crosstalk and to study the effect of repeater insertion on crosstalk, power dissipation and propagation delay.

Crosstalk is effected by transition time of the signal; length of interconnect; distance between interconnects; size of driver and receiver; pattern of input; direction of flow of signal; and clock skew. This work is based on simulating interconnects with parameters obtained from 0.13 μm process. The types of noise addressed are overshoot; undershoot and oscillatory noise. Further, to study the effect of repeater insertion on crosstalk, repeaters are inserted in one line, i.e. line A only. Uniform repeaters varying in number from 1 to 60 are each of size W_n=3.9 μm and W_p=7.8 μm. Both lines A and B are terminated by a capacitive load of 5 fF. A crosstalk noise effect is measured for line A loaded with repeaters. The number of repeater is varied for four different cases of stimulations to both lines viz. input to line A, i.e. V_A switching from low to high; input to line B, i.e. V_B switching from low to high; input to line A i.e V_A switching from low to high; input to line B, i.e. V_B switching from high to low; V_A switching from high to low and V_B at static low; V_A switching from high to low and V_B at static high.

This paper shows the prominent factors such as edge rate, length and pattern of inputs affecting the noise. It is observed that presence of inductive effects can seriously hamper the functioning of the chip. This paper further reveals that repeater insertion not only reduces the propagation delay but also crosstalk levels for coupled lines. Repeaters can be efficiently utilized for reduction of propagation delay and crosstalk noise at a trade of marginal increase in power dissipation. The power‐delay‐crosstalk‐product (PDCP) criterion is introduced as an efficient technique to insert repeater in coupled interconnects. Based on PDCP a reduction in crosstalk of about 60 times and delay of 4.2 percent is achieved at trade of 13.2 percent increase in power dissipation in comparison to PDP.

The PDCP criterion is introduced as an efficient technique to insert repeater in coupled interconnects. Instead of PDP criterion, PDCP criterion is best suited for determination of optimum number of repeaters for overall minimization of delay, power and crosstalk.

This paper proposes to study the effect of line resistance and driver width on crosstalk noise for a CMOS gate driven inductively and capacitively coupled VLSI interconnects.

The paper considers a distributed RLC interconnect topology. The interconnect length is 4 mm and far‐end capacitive loading is 30 fF. The SPICE simulation set‐up uses an IBM 0.13 μm, 1.2 V technology model. The input falling ramp has a transition time of 50 ps. The victim line is grounded through a driver resistance of 50 Ω at near end of interconnect. While observing the effect of line resistance, the aggressor driver has PMOS and NMOS widths of 70 and 30 μm, respectively, and the line resistance is varied from 0 to 500 Ω. For capturing the effect of driver width, SPICE waveforms are generated at far end of victim line for three different line resistances (R=0, 30, and 60 Ω respectively). In each case, the aggressor PMOS driver width is swept from 20 to 100 μm. The corresponding NMOS width is half of PMOS width.

It is observed that, as line resistance increases, the noise peak reduces. This is due to the fact that with increasing resistance the incident and reflected waves traveling along the line experience increasing attenuation. Hence, the waves arriving at the far‐end of the line are of smaller magnitude and larger time durations. This causes noise pulses in the lossy lines to be smaller and wider compared with those in a lossless line. The effect of driver width on noise waveforms is further observed. It is observed that, as the PMOS (and corresponding NMOS) driver width is increased, the victim line gets more prone to crosstalk noise. The crosstalk magnitude level increases alarmingly as driver width is increased, because the driver resistance decreases, which in turn increases the current driving capability of driver.

While designing coupled interconnects, driver width and line resistance play an important role in deciding the crosstalk level. An interconnect designer often increases driver width and reduces line resistance for achieving lower propagation delays. This effort may result in higher crosstalk noise in coupled interconnect. Therefore, a designer should be concerned simultaneously for crosstalk noise while reducing delays.

Most models attempting to give an account of trade-induced symmetric increase in wage inequality have abandoned the factor price equalization (FPE) framework. The present chapter retains the FPE framework and identifies a plausible route through which trade might increase wage inequality in all trading countries. A two-sector model with one constant returns sector producing basic goods and another increasing returns to scale sector producing fancy goods is developed. A quasi-linear utility function is used to capture the divide between basic and fancy goods. There are two types of productive factors, skilled and unskilled labour, and they differ with respect to their occupational options. Skilled labour can work both in the skill using fancy goods sector and in the unskilled labour using basic good producing sector, whereas unskilled labour is tied down to unskilled job. The model holds possibilities of multiple equilibria and under reasonable parameterization skill premium increases in all countries following trade.

The purpose of this paper is to explore and evaluate the performance comparison of carbon nanotubes (CNT) and nickel silicide (NiSi) nanowires interconnects as prospective alternatives to copper wire interconnects.

The increasing resistivity of the copper wire with scaling and rising demands on current density drives the need for identifying new wiring solutions. This paper explores the various alternatives to copper. The metallic bundle CNTs and NiSi nanowires are promising candidates that can potentially address the challenges faced by copper. This paper analyzes various electrical models of carbon nanotube and recently introduced novel interconnect solution using NiSi nanowires.

The theoretical studies proves CNTs and NiSi nanowires to be better alternatives against copper on the ground of performance parameters, such as effective current density, delay and power consumption. NiSi nanowire provides highest propagation speed for short wire length, and copper is the best for intermediate wire length, while bundle CNTs is faster for long wire length. NiSi nanowire has lowest power consumption than copper and CNTs.

This paper investigates, assess and compares the performance of carbon nanotubes (CNT) and NiSi nanowires interconnects as prospective alternatives to copper wire interconnects in future VLSI chips.

The purpose of this study is to alleviate the specified issues to a great extent. To promote patients’ health via early prediction of diseases, knowledge extraction using data mining approaches shows an integral part of e-health system. However, medical databases are highly imbalanced, voluminous, conflicting and complex in nature, and these can lead to erroneous diagnosis of diseases (i.e. detecting class-values of diseases). In literature, numerous standard disease decision support system (DDSS) have been proposed, but most of them are disease specific. Also, they usually suffer from several drawbacks like lack of understandability, incapability of operating rare cases, inefficiency in making quick and correct decision, etc.

Addressing the limitations of the existing systems, the present research introduces a two-step framework for designing a DDSS, in which the first step (data-level optimization) deals in identifying an optimal data-partition (Popt) for each disease data set and then the best training set for Popt in parallel manner. On the other hand, the second step explores a generic predictive model (integrating C4.5 and PRISM learners) over the discovered information for effective diagnosis of disease. The designed model is a generic one (i.e. not disease specific).

The empirical results (in terms of top three measures, namely, accuracy, true positive rate and false positive rate) obtained over 14 benchmark medical data sets (collected from https://archive.ics.uci.edu/ml) demonstrate that the hybrid model outperforms the base learners in almost all cases for initial diagnosis of the diseases. After all, the proposed DDSS may work as an e-doctor to detect diseases.

The model designed in this study is original, and the necessary parallelized methods are implemented in C on Cluster HPC machine (FUJITSU) with total 256 cores (under one Master node).

This paper aims to explore optimal pricing policies and characteristics of a two-level dual-channel supply chain under price- and delivery time-sensitive demand. Besides price of the product, the delivery lead time is also a crucial factor in customers’ purchase decisions. A longer delivery lead time would diminish customers’ acceptance and faithfulness on the online channel, while a shorter delivery lead time would lead to incorporation of a substantial amount of logistics costs. In formulation of mathematical model, the effects of delivery lead time on the manufacturer and the retailer’s pricing strategies and profits in cooperative and non-cooperative dual-channel supply chain are explained analytically.

The analytical models are formed for both non-cooperative and cooperative scenarios under inconsistent and consistent pricing. The authors examine whether revenue sharing (RS) contract or delivery cost sharing contract can solely coordinate the dual-channel supply chain. If a single contract fails, then the combination of RS contract with delivery cost sharing to achieve channel coordination is discussed.

It is found that the RS or delivery cost sharing contract cannot coordinate the channel individually but revenue and delivery cost sharing contract jointly coordinate the channel. All analytical results are illustrated numerically, along with sensitivity analysis.

There are many correlated issues that need to be further investigated. First, one good extension to this research may include the consideration of the channel structure with competitive retailers. It will be interesting to analyze the performance of coordination mechanisms by considering the retailer as a Stackelberg leader in retailing.

The findings and subsequent methodological discussions aim to provide practical guidance to retailers who are allowing customers to choose how, when and where they interact and purchase by offering a combination of websites (fully functional and mobile-enabled), catalogs and stores with increasing convergence of channels.