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This article has been withdrawn as it was published elsewhere and accidentally duplicated. The original article can be seen here: 10.1108/01445159710163481. When citing the article, please cite: David C. Whalley, Samjid H. Mannan, David J. Williams, (1997), “Anisotropic conducting adhesives for electronic assembly”, Assembly Automation, Vol. 17 Iss 1 pp. 66 - 74.

Presents some experimental and theoretical results from research exploring the design rules and relevant process parameters in the assembly of electronic components using anisotropic conductive adhesive materials. The experimental configurations studies have geometries representative of flip‐chip and micro ball grid array chip scale packaging. Evaluates a range of materials combinations, including (random filled) adhesive materials based on both thermoplastic and thermo‐setting resin systems, combined with both glass reinforced polymer printed circuit board and silver palladium thick film on ceramic substrate materials. Also presents a summary of assembly experiments which have been conducted using a specially developed instrumented assembly system. This test rig allows the measurement of the process temperatures and pressures and their relationship with the consequent bondline thickness reduction and conductivity development. Finally summarizes the capabilities of models which have been developed of the assembly process and of the final joint properties.

The dissolution rate of a solid metal such as Cu, in contact with molten solder can be calculated with the use of the Nernst‐Brenner equation. We describe how this equation should be correctly used in cases when the solder is in contact with both the base metal and any intermetallic compounds that have formed. We also show that the concentration of solute in the solder will generally lie between the metastable solubility limit and the equilibrium solubility limit, illustrating these ideas with reference to a system comprising Nb as the base metal and eutectic In‐Sn as the solder, where the concentration levels can be directly correlated to the crystal growth rate.

As the demand for flip‐chip products increases, the need for low cost high volume manufacturing processes also increases. Currently solder paste printing is the wafer bumping method of choice for device pitches down to 150‐200μm. However, limitations in print quality and stencil manufacture mean that this technology is not likely to move significantly below this pitch and new methods will be required to meet the demands predicted by the technology roadmaps. This paper describes experiments conducted on carriers made from silicon for bumping of die using solder paste. An anisotropic etching process was used to generate pockets in the silicon surface into which solder paste was printed. Die were then placed against the carrier and reflowed to transfer the solder directly to the bondpads. An assessment was carried out of the potential application and limitations of this technique for device pitches at 225 and 127μm.