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Adaptive equalization plays an important role in digital communication to reduce the distortions due to inter-symbol interference. An adaptive filter is used as an equalizer model in channel equalization. An adaptive algorithm is the heart of the adaptive filter which finds the optimum coefficients of the filter. The choice of the adaptive algorithm improves the convergence rate and minimizes the mean square error (MSE). This paper aims to propose a cat swarm optimization (CSO)-based adaptive algorithm and its modification to improve the performance of a channel equalizer.

The input digital training data are transmitted through different channel conditions. A linear transversal filter is used as a channel and equalizer model. The equalizer coefficients are trained by the proposed simplified cat swarm optimization (SCSO) algorithm to find the estimated digital training data.

The performance of the proposed SCSO algorithm is compared with particle swarm optimization (PSO)-based channel equalization. The improvement in convergence rate and MSE is verified under linear and nonlinear channel conditions with different delay spreads. The optimum parameters of the SCSO are found using simulation-based sensitivity analysis.

This paper analyzes a CSO algorithm for adaptive channel equalization and proposes a SCSO algorithm to identify the optimum coefficients of a transversal equalizer. The seeking mode process is simplified in the proposed SCSO to achieve better performance in channel equalization. The proposed SCSO algorithm guarantees minimum MSE in all independent runs, whereas in PSO, few misses are possible.

The purpose of this paper is to implement the hardware structure for radial basis function (RBF) neural network based on stochastic logic computation.

The hardware implementation of artificial neural networks (ANNs) has a complicated structure and is normally space consuming due to huge size of digital multiplication, addition/subtraction, non‐linear activation function, etc. Also the unavailability of ANN hardware at an attractive price limits its use for real time applications. In stochastic logic theory, the real numbers are converted to random streams of bits instead of a binary number. The performance of the proposed structure is analyzed using very high speed integrated circuit hardware description language.

Stochastic theory‐based arithmetic and logic approach provides a way to carry out complex computation with very simple hardware and very flexible design of the system. The Gaussian RBF for hidden layer neuron is employed using stochastic counter that reduces the hardware resources significantly. The number of hidden layer neurons in RBF neural network structure is adaptively varied to make it an intelligent system.

The paper outlines the stochastic neural computation on digital hardware for implementing radial basis neural network. The structure has considered the optimized usage of hardware resources.

Very large-scale integration (VLSI) digital signal processing became very popular and is predominantly used in several emerging applications. The optimal design of multirate filter with improvement in performance parameters such as less area, high speed and less power is the challenging task in most of the signal processing applications. This study aims to propose several effective multirate filter structures to accomplish sampling rate conversion.

The multirate filter structures considered in this work are polyphase filter and coefficient symmetry-based finite impulse response filter. The symmetry scheme particularly brings down the complexity to significant extent. To bring improvement in speed, delay registers are inserted at appropriate path with the help of pipelining and retiming scheme.

In this paper, the three tasks have been considered. First, the polyphase coefficient symmetry and modified polyphase (MP) structure is designed. Second, the pipelining is applied to the polyphase structure and the obtained results are compared with the polyphase structure. In third, retiming is applied to the polyphase structure and the performance comparison is carried out. The structures are realized for various orders, and the comparative analysis is carried out with the filter order N = 12, 30, 42, 8, 11 and 24 and the results are stated. The performance of all the accomplished structures is analyzed using Altera Quartus with the family cyclone II, device EP2C70F672C6. The results show that the multirate filter using pipelining and retiming offers better performance when examining with the conventional structures. Retimed and pipelined MP structure achieves a speed enhancement of about 33.81% when examining with the conventional polyphase (CP) structure with retiming and pipelining for N = 24 and M = 5. Likewise, the 2/3 structure of pipelined coefficient symmetry approach offers area reduction of about 54.76% over 2/3 structure of pipelined polyphase approach for N = 30 with little reduction in power. The fine grain pipelined and retimed MP structure with N = 11 and M = 3 avails critical path delay reduction of about 28.15% when examining with the corresponding fine grain pipelined and retimed CP structure.

The proposed distinct structures offer better alternative to conventional structures because of the symmetric coefficients, performance enhancement using pipelining and retiming based rate conversion structures. The suggested structures can be used for achieving different rates in software radios.