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Article
Publication date: 24 June 2020

Kanika Monga, Nitin Chaturvedi and S. Gurunarayanan

Emerging event-driven applications such as the internet-of-things requires an ultra-low power operation to prolong battery life. Shutting down non-functional block during standby…

245

Abstract

Purpose

Emerging event-driven applications such as the internet-of-things requires an ultra-low power operation to prolong battery life. Shutting down non-functional block during standby mode is an efficient way to save power. However, it results in a loss of system state, and a considerable amount of energy is required to restore the system state. Conventional state retentive flip-flops have an “Always ON” circuitry, which results in large leakage power consumption, especially during long standby periods. Therefore, this paper aims to explore the emerging non-volatile memory element spin transfer torque-magnetic tunnel junction (STT-MTJ) as one the prospective candidate to obtain a low-power solution to state retention.

Design/methodology/approach

The conventional D flip-flop is modified by using STT-MTJ to incorporate non-volatility in slave latch. Two novel designs are proposed in this paper, which can store the data of a flip-flip into the MTJs before power off and restores after power on to resume the operation from pre-standby state.

Findings

A comparison of the proposed design with the conventional state retentive flip-flop shows 100 per cent reduction in leakage power during standby mode with 66-69 per cent active power and 55-64 per cent delay overhead. Also, a comparison with existing MTJ-based non-volatile flip-flop shows a reduction in energy consumption and area overhead. Furthermore, use of a fully depleted-silicon on insulator and fin field-effect transistor substituting a complementary metal oxide semiconductor results in 70-80 per cent reduction in the total power consumption.

Originality/value

Two novel state-retentive D flip-flops using STT-MTJ are proposed in this paper, which aims to obtain zero leakage power during standby mode.

Details

Circuit World, vol. 46 no. 4
Type: Research Article
ISSN: 0305-6120

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Article
Publication date: 1 December 2003

A.K. Singh, S. Gurunarayanan, V. Ramachandran and M. Umashankar

We have solved the two‐dimensional Poisson's equation for short‐channel device under the assumption that even in the absence of drain‐to‐source voltage (VDS), a potential occurs…

215

Abstract

We have solved the two‐dimensional Poisson's equation for short‐channel device under the assumption that even in the absence of drain‐to‐source voltage (VDS), a potential occurs at the edges (source/drain) due to discontinuity at the semiconductor – channel interface in addition to built‐in‐potential. We have developed some new relations governing the operation of short‐channel devices. Analysis of relation shows that in the absence of drain‐to‐source voltage (or for very low drain‐to‐source voltage), the position of minimum potential will occur exactly at the middle of the channel. The short‐channel effect is not only observed due to applied drain‐to‐source voltage, but also due to edge potential when no bias is applied between drain and source.

Details

Microelectronics International, vol. 20 no. 3
Type: Research Article
ISSN: 1356-5362

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Article
Publication date: 16 August 2021

Umakant L. Tupe, Sachin D. Babar, Sonali P. Kadam and Parikshit N. Mahalle

Internet of Things (IoT) is an up-and-coming conception that intends to link multiple devices with each other. The aim of this study is to provide a significant analysis of Green…

253

Abstract

Purpose

Internet of Things (IoT) is an up-and-coming conception that intends to link multiple devices with each other. The aim of this study is to provide a significant analysis of Green IoT. The IoT devices sense, gather and send out significant data from their ambiance. This exchange of huge data among billions of devices demands enormous energy. Green IoT visualizes the concept of minimizing the energy consumption of IoT devices and keeping the environment safe.

Design/methodology/approach

This paper attempts to analyze diverse techniques associated with energy-efficient protocols in green IoT pertaining to machine-to-machine (M2M) communication. Here, it reviews 73 research papers and states a significant analysis. Initially, the analysis focuses on different contributions related to green energy constraints, especially energy efficiency, and different hierarchical routing protocols. Moreover, the contributions of different optimization algorithms in different state-of-the-art works are also observed and reviewed. Later the performance measures computed in entire contributions along with the energy constraints are also checked to validate the effectiveness of entire contributions. As the number of contributions to energy-efficient protocols in IoT is low, the research gap will focus on the development of intelligent energy-efficient protocols to build up green IoT.

Findings

The analysis was mainly focused on the green energy constraints and the different robust protocols and also gives information on a few powerful optimization algorithms. The parameters considered by the previous research works for improving the performance were also analyzed in this paper to get an idea for future works. Finally, the paper gives some brief description of the research gaps and challenges for future consideration that helps during the development of an energy-efficient green IoT pertaining to M2M communication.

Originality/value

To the best of the authors’ knowledge, this is the first work that reviews 65 research papers and states the significant analysis of green IoT.

Details

International Journal of Pervasive Computing and Communications, vol. 18 no. 2
Type: Research Article
ISSN: 1742-7371

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Article
Publication date: 5 October 2022

Alok Kumar Mishra, Urvashi Chopra, Vaithiyanathan D. and Baljit Kaur

A low power flip-flop circuit is designed for energy-efficient devices. Digital sequential circuits are in huge demand because every processor has most of the parts of digital…

111

Abstract

Purpose

A low power flip-flop circuit is designed for energy-efficient devices. Digital sequential circuits are in huge demand because every processor has most of the parts of digital circuit. The sequential circuits consist of a basic data storing element, a latch is used to store single bit data. The flip-flop takes a sufficient portion of the total chip area and overall power consumption as well. This study aims to the low power energy-efficient applications like laptops, mobile phones and palmtops.

Design/methodology/approach

This paper proposes a new type of flip-flop that consists of the only 16 transistors with a single-phase clock. The flip-flop has two blocks, master and slave latch. In this design, the authors have focused on only master latch, which includes a level restoring circuit. It is used to help the master latch in data retention process. The latch circuit has two inverters in back-to-back arrangement. The proposed flip-flop is implemented on 65 nm complementary metal oxide semiconductor technology using Cadence Virtuoso environment and compared with other reported flip-flops.

Findings

The proposed flip-flop architecture outperformed the peak percentage, i.e. 79.25% as compared to transmission gate flip-flop and a minimum of 20.02% compared to 18 T true single phase clocking (TSPC) improvement in terms of power. It also improved C to Q delay and power delay product. In addition, by reducing the number of transistors the total area of the proposed flip-flop is reduced by a minimum of 13.76% with respect to 18TSPC and existing flip-flop. For reliability checking the Monte Carlo simulation is performed for thousand samples and it is compared with the recently reported 18TSPC flip-flop.

Originality/value

This work is tested by using a test circuit with a load capacitor of 0.2 fF. The proposed work uses a new topology to work as master-slave. Power consumption of this technique is very less and it is best suitable for low power applications. This circuit is working properly up to 2 GHz frequency.

Details

Circuit World, vol. 50 no. 2/3
Type: Research Article
ISSN: 0305-6120

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Article
Publication date: 19 June 2020

Naga Vamsi Krishna Jasti, Srinivas Kota and Venkataraman P.B.

This paper aims to investigate the impact of simulation laboratory on continuing education engineering students’ academic performance.

329

Abstract

Purpose

This paper aims to investigate the impact of simulation laboratory on continuing education engineering students’ academic performance.

Design/methodology/approach

The investigation consists of establishing the student learning levels then mapping the student learning levels (knowledge, comprehension, application, analysis, synthesis and evaluation) through program outcomes with appropriate evaluation components. 270 continuing education students enrolled during six years were selected to be observed as part of this study. These students were divided into two subgroups, one with 135 students who were offered simulation lab (G2) and the other 135 students were not offered simulation lab (G1) in this investigation. Subsequently, a comparative analysis was carried out on these two groups to assess the student performance in multiple evaluation components with respect to student learning level and program outcome achievement.

Findings

It was identified that student performance in the application, analysis, synthesis and evaluation learning levels has improved for the group with simulation lab, and no change or minimal change was observed for the group without simulation lab. It was revealed that the simulation lab practice problems needs to be aligned with the theoretical concepts in the course to get a better performance from the students.

Originality/value

The study was conducted in one of the leading institutes with 270 students’ performance observed over a period of six years. It is the comprehensive work done on a complete program with data collated over a period of six years in multiple courses and multiple assessments.

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