Search results

The librarian and researcher have to be able to uncover specific articles in their areas of interest. This Bibliography is designed to help. Volume IV, like Volume III, contains features to help the reader to retrieve relevant literature from MCB University Press' considerable output. Each entry within has been indexed according to author(s) and the Fifth Edition of the SCIMP/SCAMP Thesaurus. The latter thus provides a full subject index to facilitate rapid retrieval. Each article or book is assigned its own unique number and this is used in both the subject and author index. This Volume indexes 29 journals indicating the depth, coverage and expansion of MCB's portfolio.

MORE than a decade ago we were assured by the then head of Imperial Chemicals Industries that the man who knows where he is going is the one who is most likely to arrive. We might venture to add as a footnote that such a man's journey will be easier, his destination more certain, if he first clears away the assorted debris that encumbers his route.

This paper reviews some continuing IBM study efforts conducted on surface mounted Leadless Chip Carrier (LCC) packaging for use in high density, high thermal stress military environments. The paper presents some designs, materials and solder joint processing considerations that can affect solder joint fatigue life. Also discussed are some thermal cycling test limitations, important properties of solder failure mechanisms and finally some technical concerns with both WS 6536E and DoD 2000 specifications as to their limitations with future surface mounted technologies.

The purpose of this paper is to identify the critical parameters that influence ball grid array and chip size package fatigue life in a random vibration environment by using a design of experimental (DOE) approach using simulation results.

The use of DOE and analysis of variation to identify the critical parameters and a response surface to generate a functional form for global modeling would be determined. Once the global modeling’s functional form was known, it can be used as boundary condition, which would be input to a local model. Knowing the critical stress, one would estimate the fatigue life from a damage model. It is the curvature of the printed wiring board in the region of the component of interest that is driving the component’s solder joint damage. The approach in this present work involves global-local modeling approaches. In the global model approach, the vibration response of the printed circuit board (PCB) will be determined.

This global model will give the response of the PCB at specific component locations of interest. This response is then fed into a local stress analysis for accurate assessment of the critical stresses in the solder joints of interest. The stresses are then fed into a fatigue damage model to predict the life.

The analysis proposed in this paper uses a failure type approach to damage analysis and involves global and local model approaches.

Provides a comprehensive review of various modelling approaches related to Just‐in‐Time (JIT) manufacturing. JIT is essentially a philosophy for reducing lead time as well as excessive work‐in‐progress inventories. Based on this concept a number of techniques have been developed for the design, planning, scheduling and control of JIT manufacturing systems. Reports on a comparative study of these approaches for JIT manufacturing along with the conventional manufacturing approaches and alternative systems for JIT manufacture. Explores future research areas.

Visual inspection remains the dominant method of assessing component lead solderability and finished board solder joint quality. In recent years the wetting balance has received much attention as an attractive alternative to the inherently subjective visual inspection method of assessing component termination solderability. Whether direct visual inspection or wetting balance methods are used, the method can be shown to be effective only if the results are in agreement with board‐level soldering performance. This paper addresses the issue of the agreement of visual board‐level solder joint quality with both visual ‘dip and look’ solderability assessment and wetting balance measurement of the components prior to board assembly. A description of visual ‘dip and look’ solderability test assessment and of wetting balance methodology for components is presented, and a compendium of wetting balance tests and indices are documented in the Appendix. The experimental strategy employed is outlined, and details of the experimental technique (including the equipment, materials and component sample preparations) are provided. The experimental results present a comparison of both ‘dip and look’ visual solderability assessment and wetting balance measures with regard to actual board‐level soldering performance. The ability of the various assessment methods to predict board level defects is also explored.

The purpose of this paper is to investigate the performance of unpaced reliable production lines that are unbalanced in terms of their mean operation times, coefficients of variation and buffer capacities.

Simulations were carried out for five‐ and eight‐station lines with various buffer capacities and degrees of means imbalance. Throughput, idle time and average buffer level performance indicators were generated and statistically analysed.

The results show that an inverted bowl allocation of mean service times, combined with a bowl configuration for coefficients of variation and a decreasing order of buffer sizes results in higher throughput and lower idle times than a balanced line counterpart. In addition, considerable reductions in average inventory levels were consistently obtained when utilizing a configuration of progressively faster stations, coupled with a bowl‐shaped pattern for coefficients of variation and an ascending buffer size order.

The results for these specific experiments imply that resources expended on trying to achieve a balanced line could be better used by seizing upon possible enhanced performance via controlled mean time, variability and buffer imbalance. Results are valid for only the line type and parameter values used (simulation results are specific and not general).

Guidelines are provided on design strategies for allocating labour and capital unevenly in unpaced lines for better performance in terms of increased throughput or lowered idle time or average buffer levels.

This paper might be viewed as one of the first simulation investigations into the performance of unpaced production lines with three sources of imbalance.

One concern that has slowed the progress of surface mounted technology, in particular leadless chip carriers, has been the question of the reliability of the surface mount attachment technology. This concern follows from the realisation that the functional reliability of surface mount technology is a very complex issue involving many not very well understood components. What is needed is a relatively simple, useful, predictive model. The model reported here sidesteps the numerous complex underlying issues, which, if considered separately, make a predictive reliability model all but impossible, by taking a purely phenomenological approach and relegating second‐order effects to a lumped empirical figure of merit.

In early 1989 the original version of the Reliability Figures of Merit (FM) for the solder attachments of surface mount (SM) assemblies was published. That version of the FM was specifically tailored for telecommunications environments. Misapplications of FMs to use environments, such as military applications and accelerated tests, pointed to a real need for generally applicable FMs. Adequate reliability of SM solder connections can only be assured with a ‘Design for Reliability’ based on solder joint behaviour and the underlying fatigue damage mechanisms. Perceived difficulties with a ‘Design for Reliability’ stem from the very complex and only partially understood nature of the interacting mechanisms underlying thermally induced solder joint fatigue, combined with the highly temperature, time, and stress‐dependent behaviour of some of the materials involved, especially solder. In this paper generic FMs are presented. These are simple design tools, easily applied by users unfamiliar with the underlying complexities of solder fatigue and the reliability assessment results are in Go/No‐go format. The oversimplifications contained in Version 1 of the FMs (originally thought necessary for simple design tools and limiting their applicability) are omitted, making these generic FMs more readily understood.

Alloy 42 and, similarly, Kovar were developed to provide metallic feed‐throughs from the interior of ceramic components to the exterior. The low coefficient of thermal expansion (CTE) of ceramic needs to be almost matched by the feed‐through metal to allow reliable hermetically sealed connections. For this purpose these alloys have served very well. However, because of its wide‐spread use for military applications, for which component hermeticity has been required, as well as because of the easier attachment of low‐CTE die to low‐CTE lead frames, Alloy 42 has found its way into plastic components with often disastrous results. When surface mount solder joints connect materials with different CTEs, global thermal expansion mismatches result. Also, if the materials to which the solder bonds have CTEs that differ from the CTE of solder, local thermal expansion mismatches result. These thermal expansion mismatches are the cause of most SM solder joint failures. Alloy 42 and Kovar not only cause significant global and local thermal expansion mismatches, but are inherently more difficult to solder because of the low solubility of nickel and iron, the main constituents of these alloys, in tin. Pull tests of solder joints show that under the best of circumstances a solder joint that includes an Alloy 42 or Kovar surface is only half as strong as one made to copper surfaces.