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The purpose of this paper is to introduce the dynamic hysteresis and losses of soft magnetic materials in numerical computation of high‐sensitive devices.

So as to do this, the authors propose to lump all the microscopic dynamic effects due to averaging and smoothing techniques that lead to the definition of a dynamic field as proposed by other contributions. In this paper, the method to implement the modified field diffusion process in finite element computations is investigated, explained, detailed and put to the test.

In order to take microscopic magnetization reversal processes and eddy currents that damp the field at the mesoscopic scale, the authors have been led to define a new dynamic property Λ representative of the magnetic structure and its easiness to change. It is involved in an additional term in both the magnetic behaviour law and the bulk and surface coupling formulations describing the physical problem in iron and at the borders.

This model can only be used for macroscopic pieces for which each dimension is bigger than at least four times the characteristic length of magnetic domains.

The originality of the paper comes from the need to investigate the possibility to predict iron losses and the corresponding dynamic hysteresis during the processing computation of power electrical devices such as accurate sensors and high‐sensitive actuators of earth leakage circuit breaker for example.

Consideration of leakage fluxes in the preliminary design stage of a machine is important for accurate determination of machine dimensions and prediction of performance characteristics. This paper aims to obtain some equations for calculating the average air gap flux density, the flux density within the magnet and the air gap leakage flux factor.

A detailed magnetic equivalent circuit (MEC) is presented for a TORUS-type non-slotted axial flux permanent magnet (TORUS-NS AFPM) machine. In this MEC, the leakage flux occurring between two adjacent magnets and the leakage fluxes taking place between the magnet and rotor iron at the interpolar, inner and outer edges of the magnets are considered. According to the proposed MEC and by using flux division law, some equations are extracted. A three-dimensional finite element method (FEM) is used to evaluate the proposed analytical equations. The study machine is a 3.7 kW and 1,400 rpm TORUS-NS AFPM machine.

The air gap leakage flux factor, the average air gap flux density and the flux density within the magnet are calculated using the proposed equations and FEM. All the results of FEM confirm the excellent accuracy of the proposed analytical method.

The new equations presented in this paper can be applied for leakage flux evaluating purposes.

The aim of the paper is to present a simple approach to modelling minor hysteresis loops in grain‐oriented steel sheets under quasi‐static and dynamic conditions. The hysteresis phenomenon is described with a recently developed hybrid model, which combines ideas inherent in the product Preisach model and the Jiles‐Atherton description. The dynamic effects due to eddy currents are taken into account in the description using a lagged response with respect to the input.

It is assumed that some model parameters might be dependent on the level of relative magnetization within the material. Their dependencies could be given as power laws. The values of scaling coefficients in power laws are determined.

A satisfactory agreement of experimental and modelled quasi‐static and dynamic hysteresis loops is obtained.

The present study provides a starting point for further verification of the approach for other classes of soft magnetic materials, which could be described with the developed model. At present, the approach to model minor loops by the update of model parameters is verified for the B‐sine excitation case.

The “branch‐and‐bound” optimization algorithm is a useful tool for recovery of the values of both model parameters and scaling coefficients as well.

The recently developed hybrid description of hysteresis phenomenon can be successfully extended to take into account symmetric minor loops. The developed approach could be a framework to develop a comprehensive description of magnetization phenomena in the future.

Pipelined analog-to-digital converters (ADCs) are widely used in electronic circuits. The purpose of this paper is to propose a new digital background calibration method to correct the capacitor mismatch, finite direct current (DC) gain and nonlinearity of residue amplifiers in pipelined ADCs.

The errors are corrected by defining new functions based on generalized Newton–Raphson algorithm. Although the functions have analytical solutions, an iterative procedure is used for calibration. To accelerate the calibration process, proper initialization for the errors is identified by using evaluation estimation block and solving inverse matrix.

Several behavioral simulations of a 12-bit 100MS/s pipelined ADC in MATLAB indicate that signal-to-(noise + distortion) ratio (SNDR) and spurious free dynamic range (SFDR) are improved from 30dB/33dB to 70dB/79dB after calibration. Calibration is achieved in approximately 2,000 clock cycles.

The digital part of the proposed method is implemented on field-programmable gate array to validate the performance of the pipelined ADC. The experimental result shows that the degradation of SNDR, SFDR, integral nonlinearity, differential nonlinearity and effective number of bits is negligible according to fixed-point operation vs floating-point in simulation results.

The novelty of this study is to use Newton–Raphson algorithm combined with appropriate initialization to reduce the number of divisions as well as calibration time, which is suitable in the recent nano-meter complementary metal oxide semiconductor technologies.

The purpose of this work in designing a wideband ring voltage-controlled oscillator (VCO) based on programmable current topology. It occupies a very tiny area yet achieving a good phase noise performance, which is suitable to be implemented in cost-effective and wideband frequency synthesizers.

The tuning range and gain are improved by dividing the VCO tuning curve into multiple curves controlled by programmable current sources without introducing additional parasitic capacitance.

Fabricated in 130-nm standard complementary metal oxide semiconductor technology and occupying an area of 0.079 mm², the VCO is tunable from 2.05 to 4.19 GHz, with a tuning percentage of 68.5 per cent. The VCO measures a phase noise performance of −96.7 dBc/Hz at an offset of 1 MHz from a 4.19 GHz carrier while consuming an average current of 6.5 mA, achieving figure of merit (FoM) and FoM_T of −158.9 and −175.6 dBc/Hz, respectively.

The proposed design uses programmable current topology without introducing parasitic capacitance, hence achieving wideband operation. It also occupies a tiny area and achieves a good phase noise performance.

This paper attempted a novel approach for system-level modeling and simulation of sigma-delta modulator for low-frequency CMOS integrated analog to digital interfaces. Comparative analysis of various architectures topologies, circuit implementation techniques are described with analytical procedure for effective selection of topologies for targeted specifications.

Virtual instruments are presented in labview environment to analyze the correlation of circuit-level non-ideal effects with key design parameters over sampling ratio, coarse quantizer bits and loop filter order. A fourth-order single-loop sigma-delta modulator is designed and verified in MATLAB simulink environment with careful selection of integrator weights to meet stable desired performance.

The proposed designed achieved SNDR of 122 dB and 20 bit resolution satisfying high-resolution requirements of low-frequency biomedical signal processing applications. Even though the simulation performed at behavioral level, the results obtained are considered as accurate, by including all non-ideal and non-linear circuit errors in simulation process.

Virtual instruments using labview environment used to analyze the correlation of circuit-level non-ideal effects with key design parameters over sampling ratio, coarse quantizer bits and loop filter order for accurate design.

In parallel sampling method, the size of the sampling capacitor is reduced to improve the bandwidth of the ADC.

Various low-power techniques for 10-bit 200MS/s pipelined analog-to-digital converter (ADC) are presented. This work comprises two techniques including parallel sampling and switched op-amp sharing technique.

This paper aims to study the effect of parallel sampling and switched op-amp sharing techniques on power consumption in pipelined ADC. In switched op-amp sharing technique, the numbers of op-amps used in the stages are reduced. Because of the reduction in the size of capacitors in parallel sampling technique and op-amps in the switched op-amp sharing technique, the power consumption of the proposed pipelined ADC is reduced to a greater extent.

Simulated the 10-bit 200MS/s pipelined ADC with complementary metal oxide semiconductor process and the simulation results shows a maximum differential non-linearity of +0.31/−0.31 LSB and the maximum integral non-linearity (of +0.74/−0.74 LSB with 62.9 dB SFDR, 55.90 dB SNDR and ENOB of 8.99 bits, respectively, for 18mW power consumption with the supply voltage of 1.8 V.

There are many types of the ADCs implemented in the mobile and wireless devices. Most of these devices are battery operated and operational at low input voltage. SAR ADC is popular for its low power operations and simple architecture. Scientists are still working to make its working faster under the same low power area. There are many SAR-ADC implemented in the past two decades, but still, there is a big room for dual SAR-ADC.

The authors are presenting a dual SAR-ADC with a smaller number of components and blocks. The proposed ultra-low-power circuit of the SAR-ADC consists of four major blocks, which include Bee-bootstrap, Spider-Latch dual comparator, dual SAR-logic and dual digital to analog converter. The authors have used the 90-nm CMOS library for the construction of the design.

The power breaks down of the comparator are dramatically improved from 0.006 to 0.003 uW. The ultimate design has 5 MHz operating frequency with 25 KS/s sampling frequency. The supply voltage is 1.2 V with 35.724 uW power consumption. Signal-to-noise and distortion ratio and spurious-free dynamic range are 65 and 84 dB, respectively. The Walden's figure of merits calculated 7.08 fj/step.

The authors are proposing two-in-one circuit for SAR-ADC named as “dual SAR-ADC”, which obeys the basic equation of duality, derived and proved under the heading of proposed solution. It shows a clear difference between the performance of two circuit-based ADC and one dual circuit ADC. The number of components is reduced by sharing the work load of some key components.

Successive Approximation Register-Analog to Digital Converter (SAR-ADC) has been achieved notable technological advancement since the past couple of decades. However, it’s not accurate in terms of size, energy, and time consumption. Many projects proposed to make it energy efficient and time-efficient. Such designs are unable to deliver two parallel outputs.

To this end, this study introduced an ultra-low-power circuitry for the two blocks (bootstrap and comparator) of 11-bit SAR-ADC. The bootstrap has three sub-parts: back-bone, left-wing and right-wing, named as bat-bootstrap. The comparator block has a circuitry of the two comparators and an amplifier, named as comp-lifier. In a bat-bootstrap, the authors plant two capacitors in the back-bone block to avoid the patristic capacitance. The switching system of the proposed design highly synchronized with the short pulses of the clocks for high accuracy. This study simulates the proposed circuits using a built-in Cadence 90 nm Complementary Metal Oxide Semiconductor library.

The results suggested that the response time of two bat-bootstrap wings and comp-lifier are 80 ns, 120 ns, and 90 ns, respectively. The supply voltage is 0.7 V, wherever the power consumption of bat-bootstrap, comp-lifier and SAR-ADC are 0.3561µW, 0.257µW and 35.76µW, respectively. Signal to Noise and Distortion Ratio is 65 dB with 5 MHz frequency and 25 KS/s sampling rate. The input referred noise of the amplifier and two comparators are 98µVrms, 224µVrms and 224µVrms, respectively.

Two basic circuit blocks for SAR-ADC are introduced, which fulfill the duality approach and delivered two outputs with highly synchronized clock pulses. The circuit sharing concept introduced for the high performance SAR-ADCs.

The ultimate aim of this study is to investigate how health information needs’ satisfaction actually makes a difference to the patients' management of a chronic clinical condition. The literature falls short of providing evidence on the interaction between patients' health information seeking behaviour and the successful management of a clinical condition. On the other hand, patient education and good information seeking practices are deemed necessary for hypertension management daily decisions.

A specially designed questionnaire study was developed: The survey design was informed by the information seeking behaviour model of Wilson for studying hypertension patients' information needs, information resources and obstacles patients face while seeking hypertension-related information. Moreover, clinical information was collected in order to make associations and inference on the impact of information seeking on patients' clinical outcomes.

The study included 111 patients submitted to the outpatient hypertension clinic of a university hospital in Athens for a 24-h ambulatory blood pressure measurement (ABPM). The analysis showed that those reporting higher satisfaction level of their information needs achieved lower values in ABPM (ABPM<130/80mmHg, p = 0.049). Stepwise the logistic regression analysis revealed three independent factors to predict the possibility of being optimally treated (ABPM<130/80mmHg). Dipping status (OR: 14.052, 95% CI: 4.229–46.688, p = 0.0001) patients with high satisfaction level of their disease (OR: 13.450, 95% CI: 1.364–132.627, p = 0.026) and interpersonal relationships were used as the main source of information (OR: 1.762, 95% CI: 1.024–3.031, p = 0.41).

Hypertensive patients with high satisfaction level of information achieve better disease control. Among different sources of information, interpersonal relationships emerge as the most appropriate factor for patients' disease control.