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Article
Publication date: 1 August 2002

A. Cordery, N. Kilbey and N. Suthiwongsunthorn

The present paper discusses the development of a test methodology for evaluation of the electrical performance of flip‐chip devices. A dedicated test chip was designed for this…

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Abstract

The present paper discusses the development of a test methodology for evaluation of the electrical performance of flip‐chip devices. A dedicated test chip was designed for this experiment. The test structure contains passive and active semiconductor devices manufactured using CMOS technology. Bond pads were designed to facilitate bumping. A Printed Circuit Board (PCB) housing the flipped devices was also designed for easy access to the individual devices. A test set‐up for measuring the structures was developed and key device parameters to monitor the electrical performance of the structures were identified.The results show that the proposed test structure is a suitable tool for determining the electrical parameters of flip‐chip devices. The experimental set‐up is universal and can be adapted to suit different custom‐designed flip‐chip test structures. In addition, the developed test set‐up is computer controlled and allows easy adaptation to different measurement techniques and devices.

Details

Microelectronics International, vol. 19 no. 2
Type: Research Article
ISSN: 1356-5362

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Article
Publication date: 1 August 2001

153

Abstract

Details

Microelectronics International, vol. 18 no. 2
Type: Research Article
ISSN: 1356-5362

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Article
Publication date: 2 January 2024

Chongbin Hou, Yang Qiu, Xingyan Zhao, Shaonan Zheng, Yuan Dong, Qize Zhong and Ting Hu

By investigating the thermal-mechanical interaction between the through silicon via (TSV) and the Cu pad, this study aimed to determine the effect of electroplating defects on the…

164

Abstract

Purpose

By investigating the thermal-mechanical interaction between the through silicon via (TSV) and the Cu pad, this study aimed to determine the effect of electroplating defects on the upper surface protrusion and internal stress distribution of the TSV at various temperatures and to provide guidelines for the positioning of TSVs and the optimization of the electroplating process.

Design/methodology/approach

A simplified model that consisted of a TSV (100 µm in diameter and 300 µm in height), a covering Cu pad (2 µm thick) and an internal drop-like electroplating defect (which had various dimensions and locations) was developed. The surface overall deformation and stress distribution of these models under various thermal conditions were analyzed and compared.

Findings

The Cu pad could barely suppress the upper surface protrusion of the TSV if the temperature was below 250 ?. Interfacial delamination started at the collar of the TSV at about 250 ? and became increasingly pronounced at higher temperatures. The electroplating defect constantly experienced the highest level of strain and stress during the temperature increase, despite its geometry or location. But as its radius expanded or its distance to the upper surface increased, the overall deformation of the upper surface and the stress concentration at the collar of the TSV showed a downward trend.

Originality/value

Previous studies have not examined the influence of the electroplating void on the thermal behavior of the TSV. However, with the proposed methodology, the strain and stress distribution of the TSV under different conditions in terms of temperature, dimension and location of the electroplating void were thoroughly investigated, which might be beneficial to the positioning of TSVs and the optimization of the electroplating process.

Details

Multidiscipline Modeling in Materials and Structures, vol. 20 no. 1
Type: Research Article
ISSN: 1573-6105

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