G.J. Jackson, M.W. Hendriksen, R.W. Kay, M. Desmulliez, R.K. Durairaj and N.N. Ekere
The study investigates the sub process behaviour in stencil printing of type‐6 and type‐7 particle size distribution (PSD) Pb‐free solder pastes to assess their printing limits.
Abstract
Purpose
The study investigates the sub process behaviour in stencil printing of type‐6 and type‐7 particle size distribution (PSD) Pb‐free solder pastes to assess their printing limits.
Design/methodology/approach
Two solder pastes were used in a design of experiments approach to find optimal printing parameters
Findings
Solder paste printing has been achieved to ultimately produce 30 μm deposits at 60 μm pitch for full area array patterns using a type‐7 Pb‐free solder paste. For a type‐6 PSD solder paste, full area array printing was limited to 50 μm deposits at 110 μm pitch. However, for peripheral printing patterns, 50 μm deposits at 90 μm pitch were obtained. The disparities in the behaviour of the two paste types at different geometries can be attributed to differences in the sub‐processes of the stencil printing. The paste release of the type‐6 paste from the stencil apertures at fine pitch was superior to the type‐7 paste, which may be attributed to the finer particle paste producing an increased drag force along the stencil aperture walls. However, the type‐7 paste was able to fill the smallest aperture openings, ultimately to 30 μm, thus producing full array printing patterns at uniquely small pitches.
Practical implications
This advancement in the stencil printing process has been made possible by refinements to both solder paste design and stencil manufacturing technology. Adjustments in the solder paste rheology have enabled successful printing at ultra fine pitch geometries. This, together with selecting appropriate printing parameters such as printing speed, pressure, print gap and separation speed, allows a practical printing process window. Moreover, advancements in stencil fabrication methods have produced “state‐of‐the‐art” stencils exhibiting very precisely defined aperture shapes, with smooth walls at very fine pitch, thus allowing for improved solder paste release at very small dimensions.
Originality/value
The results can be used to present a low cost solution for Pb‐free flip chip wafer bumping. Furthermore, the results indicate that type‐6 and type‐7 solder pastes should be applied to/selected for specific application geometries.
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M.W. Hendriksen, F.K. Frimpong and N.N. Ekere
CSP (chip scale packaging) and flip chip area array technologies are emerging within the electronics packaging industry to provide solutions capable of fulfilling the…
Abstract
CSP (chip scale packaging) and flip chip area array technologies are emerging within the electronics packaging industry to provide solutions capable of fulfilling the technological demands of computer, telecom and consumer electronic products. However, the full potential of area array attach can only be realised if the next level of interconnect is capable of supporting the fine pitch and high I/O characteristics of emerging CSP and flip chip technology. Celestica has addressed this issue by investigating next generation printed circuit board (PCB) technology, to assess the capability of organic based laminate as a high density interconnect. This paper describes the manufacturing experiments performed to produce a laser microvia interconnect solution. The mechanical performance of the interconnect is also presented to confirm its compatibility with area array assembly.
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Robert W. Kay, Gerard Cummins, Thomas Krebs, Richard Lathrop, Eitan Abraham and Marc Desmulliez
Wafer-level stencil printing of a type-6 Pb-free SAC solder paste was statistically evaluated at 200 and 150 μm pitch using three different stencil manufacturing technologies…
Abstract
Purpose
Wafer-level stencil printing of a type-6 Pb-free SAC solder paste was statistically evaluated at 200 and 150 μm pitch using three different stencil manufacturing technologies: laser cutting, DC electroforming and micro-engineered electroforming. This investigation looks at stencil differences in printability, pitch resolution, maximum achievable bump height, print co-planarity, paste release efficiency, and cleaning frequency. The paper aims to discuss these issues.
Design/methodology/approach
In this paper, the authors present a statistical evaluation of the impact of stencil technology on type-6 tin-silver-copper paste printing. The authors concentrate on performances at 200 and 150 μm pitch of full array patterns. Key evaluated criteria include achievable reflowed bump heights, deposit co-planarity, paste release efficiency, and frequency of stencil cleaning. Box plots were used to graphically view print performance over a range of aperture sizes for the three stencil types.
Findings
Fabrication technologies significantly affect print performance where the micro-engineered electroformed stencil produced the highest bump deposits and the lowest bump height deviation. Second in performance was the conventional electroformed, followed by the laser-cut stencil. Comparisons between the first and fifth consecutive print demonstrated no need for stencil cleaning in the case for the micro-engineered stencil for all but the smallest spacings between apertures. High paste transfer efficiencies, i.e. above 85 per cent, were achieved with the micro-engineered stencil using low aperture area ratios of 0.5.
Originality/value
Stencil technology influences the maximum reflowed solder bump heights achievable, and bump co-planarity. To date, no statistical analysis comparing the impact of stencil technology for wafer-level bumping has been carried out for pitches of 200 μm and below. This paper gives new insight into how stencil technology impacts the print performance for fine pitch stencil printing. The volume of data collected for this investigation enabled detailed insight into the limitations of the printing process and as a result for suitable design guidelines to be developed. The finding also shows that the accepted industry guidelines on stencil design developed by the surface mount industry can be broken if the correct stencil technology is selected, thereby increasing the potential application areas of stencil printing.
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Robert Kay and Marc Desmulliez
The purpose of this paper is to present a detailed overview of the current stencil printing process for microelectronic packaging.
Abstract
Purpose
The purpose of this paper is to present a detailed overview of the current stencil printing process for microelectronic packaging.
Design/methodology/approach
This paper gives a thorough review of stencil printing for electronic packaging including the current state of the art.
Findings
This article explains the different stencil technologies and printing materials. It then examines the various factors that determine the outcome of a successful printing process, including printing parameters, materials, apparatus and squeegees. Relevant technical innovations in the art of stencil printing for microelectronics packaging are examined as each part of the printing process is explained.
Originality/value
Stencil printing is currently the cheapest and highest throughput technique to create the mechanical and electrically conductive connections between substrates, bare die, packaged chips and discrete components. As a result, this process is used extensively in the electronic packaging industry and therefore such a review paper should be of interest to a large selection of the electronics interconnect and assembly community.
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This paper attempts to review recent advances in wire bonding using copper wire.
Abstract
Purpose
This paper attempts to review recent advances in wire bonding using copper wire.
Design/methodology/approach
Dozens of journal and conference articles published recently are reviewed.
Findings
The problems/challenges such as wire open and short tail defects, poor bondability for stitch/wedge bonds, oxidation of Cu wire, strain‐hardening effects, and stiff wire on weak support structures are briefly analysed. The solutions to the problems and recent findings/developments in wire bonding using copper wire are discussed.
Research limitations/implications
Because of page limitation of the paper, only a brief review is conducted. Further reading is needed for more details.
Originality/value
This paper attempts to provide introduction to recent developments and the trends in wire bonding using copper wire. With the references provided, readers may explore more deeply by reading the original articles.
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Z.W. Zhong, T.Y. Tee and J‐E. Luan
This paper seeks to review recent advances in wire bonding, flip chip and lead‐free solder for advanced microelectronics packaging.
Abstract
Purpose
This paper seeks to review recent advances in wire bonding, flip chip and lead‐free solder for advanced microelectronics packaging.
Design/methodology/approach
Of the 91 journal papers, 59 were published in 2005‐2007 and topics related to wire bonding, flip chip and lead‐free solder for advanced microelectronics packaging are reviewed.
Findings
Research on advanced wire bonding is continuously performed for advanced and complex applications such as stacked‐dies wire bonding, wire bonding of low‐k ultra‐fine‐pitch devices, and copper wire bonding. Owing to its many advantages, flip chip using adhesive has gained more popularity. Research on the reliability of lead‐free solder joints is being conducted world‐wide. The new challenges, solutions and new developments are discussed in this paper.
Research limitations/implications
Because of page limitation of this review paper and the large number of the journal papers available, only a brief review is conducted. Further reading is needed for more details.
Originality/value
This review paper attempts to provide introduction to recent developments and the trends in terms of the topics for advanced microelectronics packaging. With the references provided, readers may explore more deeply, focusing on a particular issue.
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This paper attempts to review recent advances in wire bonding using insulated wire and new challenges in wire bonding for advanced microelectronics packaging.
Abstract
Purpose
This paper attempts to review recent advances in wire bonding using insulated wire and new challenges in wire bonding for advanced microelectronics packaging.
Design/methodology/approach
Dozens of journal articles, conference articles and patents published or issued in 2004‐2007 are reviewed.
Findings
The advantages and problems/challenges related to wire bonding using insulated wire are briefly analysed, and several solutions to the problems and recent findings/developments related to wire bonding using insulated wire are discussed.
Research limitations/implications
Because of page limitation of the paper, only brief review is conducted. Further reading is needed for more details.
Originality/value
This paper attempts to provide introduction to recent developments and the trends in wire bonding using insulated wire. With the references provided, readers may explore more deeply by reading the original articles and patent documents.
Details
Keywords
There is increasing academic pressure on Departments of Accounting in South Africa whose academic programmes are accredited with the South African Institute of Chartered…
Abstract
There is increasing academic pressure on Departments of Accounting in South Africa whose academic programmes are accredited with the South African Institute of Chartered Accountants (SAICA). The reason for this that the academic training of potential chartered accountants has long been their main academic focus, and they often fail to do justice to their real academic mission of scholarly activity in accounting (the pursuit of science as an endeavour), which is central to the essence of a university. The quality of such departments’ research is not yet an important criterion for their prestige. However, only Departments of Accounting that develop Accounting as a social science in scholarly activity in accounting deserve international recognition. This empirical study attempts to convince Departments of Accounting, particularly those whose academic programmes are accredited by SAICA, to embark on scholarly activity in accounting as soon as possible.