Ming‐Chih Yew, Chien‐Chia Chiu, Shu‐Ming Chang and Kuo‐Ning Chiang
The coefficient of thermal expansion (CTE) mismatch between silicon and organic printed circuit board (PCB) materials causes a reliability issue for ball grid array type…
Abstract
Purpose
The coefficient of thermal expansion (CTE) mismatch between silicon and organic printed circuit board (PCB) materials causes a reliability issue for ball grid array type electronic packages. This makes it difficult for conventional wafer level chip scaled packaging (WLCSP) with large die to satisfy the reliability requirements. Therefore, in this study a novel solder joint protection‐WLCSP (SJP‐WLCSP) structure is proposed to overcome the reliability issue.
Design/methodology/approach
The SJP‐WLCSP makes use of a delaminating layer to reduce the problem of CTE mismatch. In the SJP‐WLCSP, a delaminating layer is interposed between the top layer of the chip and the bottom insulating layer of the redistribution copper metal traces. As a result, the stress on the solder joints can be released by allowing cracks to form in the delaminating layer.
Findings
To elucidate the thermo‐mechanical behaviour of tin‐lead eutectic solder joints and copper traces, a non‐linear analysis, based on a 3D finite element (FE) model, under accelerated thermal test loadings was carried out. The maximum equivalent stress/strain in the solder joints predicted by the FE simulation were found to diminish significantly when applying the delaminating layer. In addition, parametric FE analysis was also applied in this study, and based on the design concepts within this study, a robust novel SJP‐WLCSP could be achieved.
Originality/value
In this work, a new packaging concept with high reliability, low cost and easy fabrication was developed to reduce the shear stress in the solder joints due to the CTE mismatch between silicon chips and organic PCBs.
Details
Keywords
Ming‐Chih Yew, Mars Tsai, Dyi‐Chung Hu, Wen‐Kun Yang and Kuo‐Ning Chiang
The wafer level package (WLP) is a cost‐effective solution for electronic packaging and has been increasingly applied in recent years. The purpose of this paper is to propose a…
Abstract
Purpose
The wafer level package (WLP) is a cost‐effective solution for electronic packaging and has been increasingly applied in recent years. The purpose of this paper is to propose a newly developed packaging technology, based on the concepts of the WLP, the panel base package (PBP) technology, in order to further obtain the capability of signal fan‐out for fine‐pitched integrated circuits (ICc).
Design/methodology/approach
In the PBP, the filler material is selected to fill the trench around the chip and provide a smooth surface for the redistribution lines. Therefore, the solder bumps could be located on both the filler and the chip surface and the pitch of the chip side is fanned‐out. The design concept and the manufacturing process of the PBP would first be described in this study. The three‐dimensional finite element model is established based on the real testing sample and the thermo‐mechanical behavior of the PBP is simulated.
Findings
It is found that the solder joint reliability of the PBP can be highly improved because of the applied stress buffer layer. However, the accumulated stress/strain from the coefficient of thermal expansion mismatch may transfer to the metal lines in package. In order to enhance the robustness of the redistribution lines, the bypassed type interconnect is suggested. Moreover, the trace/pad connecting junction and the conductive via which have smooth outline are preferred to avoid stress concentration effects.
Originality/value
In this paper, a low‐cost and short time‐to‐market packaging technology is proposed which is especially suitable for high density IC devices. The PBP technology has the ability to meet the requirements of major reliability testing conditions and it will have a high potential for application in the near future.
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Keywords
Kuo-Ning Liu and Clark Hu
This study aims to address research gaps by constructing critical success factors (CSFs) in the context of green hotel investment in Taiwan. It contributes to the domain knowledge…
Abstract
Purpose
This study aims to address research gaps by constructing critical success factors (CSFs) in the context of green hotel investment in Taiwan. It contributes to the domain knowledge to cultivate Taiwan’s green hotel development in the future.
Design/methodology/approach
The authors secured 20 prominent green hotel management/owners/architects as crucial informants. The first stage used the Delphi method to collect expert opinions (i.e. CSFs) and the second stage applied the analytic hierarchy process to analyze the importance of CSFs.
Findings
The results show that the “financial investment benefits” is considered the most crucial success factor for the green hotel investment. However, to balance long-term economic development with environmental impact, green hotel investors should consider other aspects of the research to sustain future financial performance returns.
Research limitations/implications
Further studies should consider regional characteristics to accommodate geographic/social differences and hotel types to explore possible CSFs for the green hotel investment. The authors suggest including panel experts from government officials and prominent scholars to represent a broader but different view on subject matters. They also offer implications for investors’ governmental policies, hotelier cognition and customer-related aspects in green hotel investment.
Originality/value
This study built a hierarchical framework based on the CSF concept by evaluating priority differences between hotel management and hotel owners/architects. Such findings help investors’ effective decision-making through considering factors’ relative importance for green hotel investments.