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While promising significant improvements in the cost and performance of electronic systems, the advent of new area array packaging concepts such as the BGA and newer area array CSPs has placed significant new demands on the substrates used in their interconnection. New methods such as build‐up multilayers and micro vias and co‐lamination of inner layers have been described and implemented by a number of different firms in an attempt to address this important issue. One such method employs simple double‐sided plated through hole flex circuits and the use of conductive pastes and bondplies to provide reliable electrical and mechanical connection between layers during a simple lamination cycle. The process, briefly described herein as a co‐laminated multilayer flex, is detailed in terms of both process steps and manufacturing flow. The structure of the interconnection substrate is also modeled and examined to determine its electrical performance potential according to electrical modeling software. Finally, detailed are the performance of the structure in reliability testing and an analysis of the expected design and performance advantages that might be obtained by such type constructions in combination with BGAs and area array CSPs.