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Owing to recent challenges of CMOS manufacturing and power consumption in silicon technologies among alternative technologies, Nanomagnetic logic (NML) is one of the most promising technologies, so it was selected for this study. NML is non-volatile with ultra-low power dissipation that operates at room temperature. This paper aims to propose novel implementation of 2% and 4% multiplexers (MUXs) in NML technology.

The proposed multiplexers in NML technology are verified by HDL-based simulators. In addition, this study estimated area and power dissipation of the proposed design to compare and approve the promising improvements in comparison to other similar NML implementations.

The results show the remarkable improvements in terms of APDP term in comparison to the recent proposed MUXs in NML technology which are reported in Table 2. The proposed implementation of the MUX in NML is designed in three-dimensional layout to improve interconnection complexity which is an integration challenge. Also, by facilitating the routing signals and total wire length needed for clock signals, the negative impact of the power dissipated in clock wires is improved.

These findings would appeal to a broad audience, such as the readership of Microelectronics International Journal. The authors confirm that this work is original and has not been published elsewhere nor is it currently under consideration for publication elsewhere. All authors have approved the paper and agreed with submission to Microelectronics International Journal. The authors have read and have abided by the statement of ethical standards for manuscripts submitted to Microelectronics International Journal. The authors have no conflict of interest to declare.

Quantum-dot cellular automata (QCA) has attracted computer scientists as new emerging nanotechnology for replacement the current CMOS technology because it has unique characteristics such as high frequency, extremely small feature size and low power consumption. The main building blocks in QCA are the majority gate and inverter so any Boolean function can be represented using these gates. Many important circuits were the target for implemented in this technology in an optimal form, such as random-access memory (RAM) cell. QCA-RAM cells were introduced in literature with different forms but most of them are not optimized enough. This paper aims to demonstrate QCA inherent capabilities that can facilitate the design of many important gates such as the XOR gate and multiplexer (MUX) without following any Boolean function to get an optimum design in terms of complexity and delay.

In this paper, a novel structure of QCA-MUX in an optimal form will be used to design two unique structures of a RAM cell. The proposed RAM cells are the lowest cost required compared with different counterparts. The presented RAM cells used a new approach that follows the new suggested block diagram. The presented circuits are simulated and tested with QCADesigner and QCAPro tools.

The comparison of the proposed circuits with the previously reported in the literature show noticeable improvements in speed, area, and the number of cells. The cost function analysis results for the proposed RAM cells show significant improvement compared to older circuits.

A novel structure of QCA-MUX in an optimal form will be used to design two unique structures of a RAM cell.

The high demand for fast, energy-efficient, compact computational blocks in digital electronics has led the researchers to use approximate computing in applications where inaccuracy of outputs is tolerable. The purpose of this paper is to present two ultra-high-speed current-mode approximate full adders (FA) by using carbon nanotube field-effect transistors.

Instead of using threshold detectors, which are common elements in current-mode logic, diodes are used to stabilize voltage. Zener diodes and ultra-low-power diodes are used within the first and second proposed designs, respectively. This innovation eliminates threshold detectors from critical path and makes it shorter. Then, the new adders are employed in the image processing application of Laplace filter, which detects edges in an image.

Simulation results demonstrate very high-speed operation for the first and second proposed designs, which are, respectively, 44.7 per cent and 21.6 per cent faster than the next high-speed adder cell. In addition, they make a reasonable compromise between power-delay product (PDP) and other important evaluating factors in the context of approximate computing. They have very few transistors and very low total error distance. In addition, they do not propagate error to higher bit positions by generating output carry correctly. According to the investigations, up to four inexact FA can be used in the Laplace filter computations without a significant image quality loss. The employment of the first and second proposed designs results in 42.4 per cent and 32.2 per cent PDP reduction compared to when no approximate FA are used in an 8-bit ripple adder.

Two new current-mode inexact FA are presented. They use diodes as voltage regulators to design current-mode approximate full-adders with very short critical path for the first time.