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The purpose of this paper is to describe a novel method for the manufacture of aluminum rigid‐flex circuit assemblies without the use of solder.

The approach involves the use of an aluminum base material and the embedding of components, while avoiding the use of solder in the assembly process.

The new methods and proposed structures address the key manufacturing problems that have vexed users for many years, while simultaneously addressing the challenge of thermal management. They also offer the advantage of enhanced reliability by avoiding the need for high temperatures used in soldering.

While examples of the process and its benefits have been demonstrated, further work is ongoing to expand applicability.

The paper begins with an overview of previous work in this area and then moves on to what is currently being implemented via the new technology. A novel method is described for the creation of potentially more cost‐effective and reliable rigid flex assemblies, which would be suitable for use in a wide range of products, from consumer to high‐reliability automotive, military and aerospace.

The purpose of this paper is to provide a historical perspective and framework for appreciating the evolution of 3D interconnection technologies from past to present.

A literature and patent search was performed to find the origins of 3D interconnections to find and credit work that was performed in the early electronics industry which presaged the development of the current generation 3D solutions.

The origins of 3D interconnections have roots that date to the beginnings of electronic interconnections if the earlier solutions are viewed in proper perspective. For example, early telegraphy and telephony interconnections strung from pole to pole across large expanses of terrain were clearly 3D interconnections on a very macro scale but those solutions scaled down are not that dissimilar to what is being done today in some advanced interconnection technologies.

The pioneers of the electronics industry broke a trail which has been widened, paved and branched by all who have followed them. Granted that the branches have led to new high‐worth discoveries but acknowledging the past and taking instruction from it is important, even necessary, to assure that future developments do not continually “reinvent the wheel”.

The paper traces, in brief fashion, the history of 3D interconnections providing examples of solutions which predate some of the current generation solutions which appear, in some cases, quite similar to those developed or proposed nearly half century ago. Knowing the past is vital to understanding and shaping the future.

While promising significant improvements in the cost and performance of electronic systems, the advent of new area array packaging concepts such as the BGA and newer area array CSPs has placed significant new demands on the substrates used in their interconnection. New methods such as build‐up multilayers and micro vias and co‐lamination of inner layers have been described and implemented by a number of different firms in an attempt to address this important issue. One such method employs simple double‐sided plated through hole flex circuits and the use of conductive pastes and bondplies to provide reliable electrical and mechanical connection between layers during a simple lamination cycle. The process, briefly described herein as a co‐laminated multilayer flex, is detailed in terms of both process steps and manufacturing flow. The structure of the interconnection substrate is also modeled and examined to determine its electrical performance potential according to electrical modeling software. Finally, detailed are the performance of the structure in reliability testing and an analysis of the expected design and performance advantages that might be obtained by such type constructions in combination with BGAs and area array CSPs.

“A patterned arrangement of printed wiring utilizing flexible base material with or without flexible coverlayers”. The balance of this brief article will hopefully serve to help the reader understand this remarkable interconnection technology and appreciate just how widely the technology can be applied.

To provide an overview of a process for making proper selection of base materials for use in the manufacture of flexible circuits.

The paper provides an introductory review of the desirable attributes for flexible circuit substrates and includes a description of the attribute and its specific role and impact on the finished product.

The paper highlights the importance of making informed materials choices in flexible circuit manufacture. Flexible circuits are an increasingly important member of the family of electronic interconnection technologies and are also the fastest growing. A variety of materials can be used for flexible circuit construction, however, the choice must be tempered by the manufacturing and assembly processes and the application of the finished product.

The paper provides a limited overview of the desirable properties of flexible circuit materials and is designed to provide initial background and guidance for making more informed decisions about material choices.

This paper provides an overview of the various factors that should be considered in advance of committing to a flex circuit design.

Tin‐lead solder has been the primary method for connecting electronic components to printed circuit boards since near the time of its inception. Over the last 60 years, solder has proven a viable assembly method over that time and there is a deep understanding of the technology won over years of practice. However, the European Union has banned the use of lead in electronic solder, based on the misguided assumption that lead in electronic solder represented a risk to human health. Aims to describe a new approach to manufacturing electronic assemblies without the use of solder.

The paper discusses how the new era of lead‐free solder has resulted in a host of new problems for the electronics industry, many of which had not been experienced when elemental lead was included in the solder alloy.

Electronics assembly technology literature is rife with articles and papers citing the problems or challenges of lead‐free assembly and proposing new or improved solutions or investigative tool to better unearth the problems of lead‐free. The new process has come to be known as the Occam process, named to honor the fourteenth century English philosopher and logician, William of Occam, whose rigorous thinking and arguments in favor of finding the simplest possible solution served as the inspiration and catalyst for the new approach.

The paper describes a new approach to manufacturing electronic assemblies without the use of solder.

To review the challenges confronting the electronics interconnection industry as it transitions into the gigahertz frequency range and to describe novel prospective solutions designed to circumvent the problems by means of alternative interconnection architectures while remaining within the confines of the existing manufacturing infrastructure.

The paper has been written in a manner so as to provide first a brief review of the history of interconnections as background reference, providing access and understanding to a broader readership of the significance of the area of investigation. From there, the paper describes the problems facing electronic circuit manufactures relative to the serious matter of assuring signal integrity of high speed interconnections. It then goes on to describe a general class of prospective solutions, which can be implemented through simple architectural changes in design and manufacture. Finally, the paper describes a prototype system which was fabricated using the concepts and the first‐order findings are provided.

From operation of the prototype system, it was found that the concepts, relative to PCB architectural changes prescribed in the paper are capable of delivering performance levels beyond what is accepted when using traditional interconnection modalities. The 10 Gbps backplane prototype has proved capable of sending a 100 mV peak‐to‐peak signal a distance of 75 cm through a two wire single differential pair which pass through two industry standard connectors. The signal generated has a ∼65 percent margin indicating it could go much further and determining the limits an object of future study. The modulation is standard NRZ. With only two wires there was no cross talk in the system, however, the next stage of investigation will consist of a multi‐device assembly to see what cross talk effect there might be, if any.

The chief value of the paper resides in its disclosure of novel approaches to electronic interconnection involving simple changes in circuit architectural structures which extend the signal performance limits of copper interconnections, well beyond present consensus expectations of industry. Moreover, the paper provides first experimental results of the technology in actual operation as proof of concept.

The concept of packaging integrated circuits while they are still in wafer form has captured the imagination of semiconductor manufacturers and packagers around the globe. One such concept, referred to as wide area vertical expansion (WAVE^TM) technology promises to provide a relatively easy method for cost effectively interconnecting ICs while still on the wafer. Moreover the fundamental technology is amenable to the production of “virtual wafers” where individual IC chips can be assembled en masse. The virtual wafer variation also allows for die shrink to occur, while the IC package footprint remains constant. The technology is based on concepts that allow for the mass assembly and production of compliant packages both directly on the wafer and in “virtual wafer” format where individual chips are bonded directly to the flexible pellicle. This paper examines this important new packaging technology concept in terms of the process and device and the implications and future directions the technology is likely to take.

The drive to increase the functionality and performance of electronic products has resulted in the need to increase the density of every element of the electronics assembly from the silicon chip, which has relentlessly reduced in size, to the printed circuits used in their interconnection. Accompanying the reduction in feature sizes on IC chips has been an explosion in pin counts, especially in high‐end microprocessors. The challenge thus falls to the electronics interconnection and packaging industry to allow the pace to continue. Reviews strategies being either proposed or used to meet the challenge of high‐density interconnection at both chip package and next level substrate.