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The purpose of this paper is to focus on through‐silicon via (TSV), with a new concept that every chip or interposer could have two surfaces with circuits. Emphasis is placed on the 3D IC integration, especially the interposer (both active and passive) technologies and their roadmaps. The origin of 3D integration is also briefly presented.

This design addresses the electronic packaging of 3D IC integration with a passive TSV interposer for high‐power, high‐performance, high pin‐count, ultra fine‐pitch, small real‐estate, and low‐cost applications. To achieve this, the design uses chip‐to‐chip interconnections through a passive TSV interposer in a 3D IC integration system‐in‐package (SiP) format with excellent thermal management.

A generic, low‐cost and thermal‐enhanced 3D IC integration SiP with a passive interposer has been proposed for high‐performance applications. Also, the origin of 3D integration and the overview and outlook of 3D Si integration and 3D IC integration have been presented and discussed. Some important results and recommendations are summarized: the TSV/redistribution layer (RDL)/integrated passive devices passive interposer, which supports the high‐power chips on top and low‐power chips at its bottom, is the gut and workhorse of the current 3D IC integration design; with the passive interposer, it is not necessary to “dig” holes on the active chips. In fact, try to avoid making TSVs in the active chips; the passive interposer provides flexible coupling for whatever chips are available and/or necessary, and enhances the functionality and possibly the routings (shorter); with the passive interposer, the TSV manufacturing cost is lower because the requirement of TSV manufacturing yield is too high (>99.99 percent) for the active chips to bear additional costs due to TSV manufacturing yield loss; with the passive interposer, wafer thinning and thin‐wafer handling costs (for the interposer) are lower because these are not needed for the active chips and thus adds no cost due to yield loss; with the current designs, all the chips are bare; the packaging cost for individual chips is eliminated; more than 90 percent of heat from the 3D IC integration SiP is dissipated from the backside of high‐power chips using a thermal interface material and heat spreader/sink; the appearance and footprint of current 3D IC integration SiP designs are very attractive to integrated device manufactures, original equipment manufactures, and electronics manufacturing services (EMS) because they are standard packages; and underfills between the copper‐filled TSV interposer and the high‐ and low‐power chips are recommended to reduce creep damage of the lead‐free microbump solder joints and prolong their lives.

The paper's findings will be very useful to the electronic industry.

The solder‐joint reliability of solder‐bumped wafer level chip scale package (WLCSP) on microvia build‐up printed circuit board (PCB) subjected to thermal cycling conditions is investigated in this study. The 62Sn36Pb2Ag solder joints are assumed to be: an elastic material; an elastic‐plastic material; and a creep material which obey the Garofalo‐Arrhenius steady‐state creep constitutive law. The stress and strain in the corner solder joint of the WLCSP assembly are presented and compared for these three material models. Also, the results presented herein will be compared with that from creep analysis of the WLCSP on PCB without microvia build‐up layer.

A family of cavity‐down plastic ball grid array (PBGA) packages have been designed by split via connection (SVC) and split wrap around (SWA) methods. Because of the special designs, these packages consist of a single core of organic material and two‐metal layers of copper and are manufactured with the conventional printed circuit board (PCB) process at very low cost. The electrical performances of the packages are studied by both numerical simulations and experimental measurements. Parasitic parameters are extracted from time domain reflectometer (TDR) and time domain transmission (TDT) measurements. Cross‐talk and simultaneous switch output (SSO) noise of the packages are also investigated.

In this paper, a computational analysis is presented for the comparison of wafer level chip scale package‐on‐build‐up PCB assemblies with various solders and microvia configurations. The printed circuit board of the assembly has one build‐up layer on one side. For comparison, the board with two build‐up layers on the same side is studied as well. Furthermore, two solder joint materials, namely, 62Sn–2Ag–36Pb and 96.5Sn–3.5Ag are studied for comparison. The assembly is simulated by a finite element model and the model is analyzed under thermal cyclic loading. A comprehensive stress analysis is performed and comparisons are made for assembly deformation, stress/strain ranges, and creep responses.

NuBGA is a low‐cost, single‐core, two‐metal layer, cavity‐down plastic ball grid array package. With special design concepts, NuBGA provides electrical and thermal enhancements for electronic packaging applications. The concepts of these innovative designs are briefly described. Thermal resistance of junction to air is investigated first by finite element simulations, and the results are then compared to experimental measurements. Also, thermal measurements are carried out for both with, and without, heat sink attachment. Geometric dependence of thermal resistance on structural parameters such as thickness of the copper heat spreader and organic substrate, power and ground planes in printed circuit board (PCB), and the size of PCB are also discussed.

The lead‐free solder joint reliability of several printed circuit board mounted high‐density packages, when subjected to temperature cycling was investigated by finite element modelling. The packages were a 256‐pin plastic ball grid array (PBGA), a 388‐pin PBGA, and a 1657‐pin ceramic column grid array. Emphasis was placed on the determination of the creep responses (e.g. stress, strain, and strain energy density) of the lead‐free solder joints of these packages.

Temperature cycling tests, and statistical analysis of the results, for various high‐density packages on printed‐circuit boards with Sn‐Cu hot‐air solder levelling, electroless nickel‐immersion gold, and organic solder preservative finishes are investigated in this study. Emphasis is placed on the determination of the life distribution and reliability of the lead‐free solder joints of these high‐density package assemblies while they are subjected to temperature cycling conditions. A data acquisition system, the relevant failure criterion, and the data extraction method will be presented and examined. The life test data are best fitted to the Weibull distribution. Also, the sample mean, population mean, sample characteristic life, true characteristic life, sample Weibull slope, and true Weibull slope for some of the high‐density packages are provided and discussed. Furthermore, the relationship between the reliability and the confidence limits for a life distribution is established. Finally, the confidence levels for comparing the quality (mean life) of lead‐free solder joints of high‐density packages are determined.

Failure analyses of the lead‐free and SnPb solder joints of high‐density packages such as the plastic ball grid array and the ceramic column grid array soldered on SnCu hot‐air solder levelling electroless nickel‐immersion gold or NiAu, and organic solderability preservative Entek printed circuit boards are presented. Emphasis is placed on determining the failure locations, failure modes, and intermetallic compound composition for these high‐density packages' solder joints after they have been through 7,500 cycles of temperature cycling. The present results will be compared with those obtained from temperature cycling and finite element analysis.

The High Density Packaging Users Group Consortium has conducted a study of process development and solder‐joint reliability of high‐density packages on printed circuit boards (PCB) using a low‐melting temperature lead‐free solder. The purpose of this paper is to investigate the reliability tests (e.g. temperature cycling and shock and vibration) and failure analysis (FA) of high‐density packages on PCB with the low‐melting temperature lead‐free solder (Sn‐57 wt%Bi‐1 wt%Ag).

The design for reliability, materials, and assembly process aspects of the project have been discussed in “Design, materials, and assembly process of high‐density packages with a low‐temperature lead‐free solder (SnBiAg)” also published in this journal issue. In this study, reliability tests (e.g. temperature cycling and shock and vibration) and FA of high‐density packages on PCB with the low‐melting temperature lead‐free solder (Sn‐57 wt%Bi‐1 wt%Ag) are investigated.

Lead‐free solder‐joint reliability of high‐density packages, such as the PBGA388, PBGA256, PBGA208, PBGA196, PBGA172, PQFP80, and TSSOP56 were determined by temperature cycling, shock, and vibration tests. Temperature cycling test data for over 8,100 cycles between 0 and 100°C in a 44 min. cycle were statistically analyzed. Shock and vibration test data based on the HP Standard Class Bi‐II Products SPEC have also been reported.

Currently there is a lack of experimental and simulation data and field experience in respect of one of the critical issues for industry – that of solder joint reliability in lead‐free soldering. The paper contains some important research results and recommendations.

The purpose of this paper is to discuss the design, materials, and assembly process aspects of a study, conducted by The High Density Packaging Users Group Consortium, into process development and solder joint reliability of high‐density packages on printed circuit boards using a low‐melting temperature lead‐free solder (Sn‐57 wt%Bi‐1 wt%Ag).

The components studied include several SMT package types and various lead configurations. The assembly process addresses the low‐temperature lead‐free assembly process, inspection and analysis of these boards and packages.

It was found that, the assembly process of the SnBiAg lead‐free test boards is very robust and the assembly yield is almost 100 percent.

The paper is of value by presenting a description of the rationale and material set used for an experiment to test SMT assembly and reliability characteristics using the 57Bi‐42Sn‐1Ag alloy, which has a melting point of 139°C.