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The subtractive method is widely used to produce high‐density PWBs. It is generally accepted that a pattern pitch of 100 microns or less cannot be achieved by the subtractive method because of the thickness of the copper layer to be etched. We report here on experiments to investigate the relationship between the pattern pitch of a circuit formed by the subtractive method and the required thickness of the copper layer. We have also determined the allowable thickness of the copper layer, plating layer, and copper foil layer for achieving a pattern pitch of 100 microns (L/S = 50/50 microns) or less.

As CPUs increase in performance, the number of passive components on the surface of circuit boards also increases dramatically. To reduce the number of components, as well as improve the electrical performance (i.e. reduce inductance), designers are increasingly embedding capacitive layers in the PCB. The majority of the products in use utilize reinforced epoxy laminates. These products are relatively easy to handle, but the thickness and Dk limit the effectiveness of the layer to perform as a capacitor. Other materials are being developed that are thinner (and thus increase capacitance), but either have problems with dielectric breakdown strength, handling or offer only a marginal improvement over existing materials. This paper describes new non‐reinforced substrates for use as embedded capacitance layers that address these issues. The material selection process, substrate processing and electrical performance are reviewed.