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Article
Publication date: 1 August 2016

Ying-Shieh Kung, Seng-Chi Chen, Jin-Mu Lin and Tsung-Chun Tseng

The purpose of this paper is to integrate the function of a speed controller for induction motor (IM) drive, such as the speed PI controller, the current vector controller, the…

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Abstract

Purpose

The purpose of this paper is to integrate the function of a speed controller for induction motor (IM) drive, such as the speed PI controller, the current vector controller, the slip speed estimator, the space vector pulse width modulation scheme, the quadrature encoder pulse, and analog to digital converter interface circuit, etc. into one field programmable gate array (FPGA).

Design/methodology/approach

First, the mathematical modeling of an IM drive, the field-oriented control algorithm, and PI controller are derived. Second, the very high speed IC hardware description language (VHDL) is adopted to describe the behavior of the algorithms above. Third, based on electronic design automation simulator link, a co-simulation work constructed by ModelSim and Simulink is applied to verify the proposed VHDL code for the speed controller intellectual properties (IP). Finally, the developed VHDL code will be downloaded to the FPGA for further control the IM drive.

Findings

In realization aspect, it only needs 5,590 LEs, 196,608 RAM bits, and 14 embedded 9-bit multipliers in FPGA to build up a speed control IP. In computational power aspect, the operation time to complete the computation of the PI controller, the slip speed estimator, the current vector controller are only 0.28 μs, 0.72 μs, and 0.96 μs, respectively.

Practical implications

Fast computation in FPGA can speed up the speed response of IM drive system to increase the running performance.

Originality/value

This is the first time to realize all the function of a speed controller for IM drive within one FPGA.

Details

Engineering Computations, vol. 33 no. 6
Type: Research Article
ISSN: 0264-4401

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