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Article
Publication date: 3 April 2017

Mei-Ling Wu and Jia-Shen Lan

The purpose of this study was to investigate the changes in solder joint stress when subjected to mechanical bending. The analytical theory pertaining to the stresses in the…

317

Abstract

Purpose

The purpose of this study was to investigate the changes in solder joint stress when subjected to mechanical bending. The analytical theory pertaining to the stresses in the solder joint between the components (including the molding compound, the chip and the substrate) was described, and the printed circuit board (PCB) with a discontinuity function when the PCB assembly is subjected to mechanical bending was developed. Thus, the findings reported here may lead to a better understanding of the solder joint failure based on the Physics of Failure model.

Design/methodology/approach

This paper discusses the analytical model for calculating the stress in solder joints, as well as presents a simulation model that can be used for calculating the strain energy density of solder joint. First, the multilayer plate theory is used in discussing the composite material for the component, including the molding compound, the silicon chip and the substrate, or the PCB, including the copper layers, the fiber and the epoxy. Finally, the complete structure of the analytical model developed as a part of this current work is presented.

Findings

For the analytical model of multilayer structures in which the interconnection layer is discrete, mechanical bending has been modeled with respect to varying silicon chip length. The analytical model that describes the stress of the outermost solder joint experiences is chosen, as this is the typical solder joint failure. The analytical model can be applied to discrete solder joints, which are evaluated by calculating the matrix form. Owing to its use of the matrix equation, the analytical model can be highly combinatorial and thus more capable of calculating the solution.

Research limitations/implications

The analytical solution based on a simple concept was presented and validated using the finite element model for the stress experienced by solder joints subjected to mechanical bending. To verify that the simulation represents a real PCB case, the authors use the finite element method (FEM) to compare their case with the multilayer plate theory. Owing to the good agreement between the theory and simulation results, the authors conclude that the multilayer plate theory can be correctly applied in multilayer PCB and be used in an analytical model for the PCB assembly subjected to mechanical bending.

Practical implications

Owing to the good agreement between the theory and simulation results, the authors conclude that the multilayer plate theory can be correctly applied in multilayer PCB and be used in an analytical model for the PCB assembly subjected to mechanical bending.

Social implications

The analytical model is validated with the FEM model and provides the way to physically examine the solder joint failure mechanism. In this paper, the analytical model is developed as a means to assess the solder joint stress subjected to mechanical bending.

Originality/value

The analytical model treats the solder joint as discrete and has been successfully validated against the finite element model. The complete structure model (the second analytical model) is presented to discuss the effects of varying silicon chip length on the normal stress in solder joints. When the silicon chip length exceeds to 80 per cent of the total package length, the stress of the outermost solder joint increases rapidly. The design analysis findings have suggested that the failure of the outermost solder joint subjected to mechanical bending on the PCB assembly can be reduced by analyzing the analytical model.

Details

Soldering & Surface Mount Technology, vol. 29 no. 2
Type: Research Article
ISSN: 0954-0911

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Article
Publication date: 5 September 2016

Mei-Ling Wu and Jia-Shen Lan

This paper aims to develop the thermal resistance network model based on the heat dissipation paths from the multi-die stack to the ambient and takes into account the composite…

277

Abstract

Purpose

This paper aims to develop the thermal resistance network model based on the heat dissipation paths from the multi-die stack to the ambient and takes into account the composite effects of the thermal spreading resistance and one-dimensional (1D) thermal resistance. The thermal spreading resistance comprises majority of the thermal resistance when heat flows in the horizontal direction of a large plate. The present study investigates the role of determining the temperature increase compared to the thermal resistances intrinsic to the 3D technology, including the thermal resistances of bonding layers and through silicon vias (TSVs).

Design/methodology/approach

This paper presents an effective method that can be applied to predict the thermal failure of the heat source of silicon chips. An analytical model of the 3D integrated circuit (IC) package, including the full structure, is developed to estimate the temperature of stacked chips. Two fundamental theories are used in this paper – Laplace’s equation and the thermal resistance network – to calculate 1D thermal resistance and thermal spreading resistance on the 3D IC package.

Findings

This paper provides a comprehensive model of the 3D IC package, thus improving the existing analytical approach for predicting the temperature of the heat source on the chip for the 3D IC package.

Research limitations/implications

Based on the aforementioned shortcomings, the present study aims to determine if the use of an analytical resistance model would improve the handling of a temperature increase on the silicon chips in a 3D IC package. To achieve this aim, a simple rectangular plate is utilized to analyze the temperature of the heat source when applying the heat flux on the area of the heat source. Next, the analytical model of a pure plate is applied to the 3D IC package, and the temperature increase is analyzed and discussed.

Practical implications

The main contribution of this paper is the use of a simple concept and a theoretical resistance network model to improve the current understanding of thermal failure by redesigning the parameters or materials of a printed circuit board.

Social implications

In this paper, an analytical model of a 3D IC package was proposed based on the calculation of the thermal resistance and the analysis of the network model.

Originality/value

The aim of this work was to estimate the mean temperature of the silicon chips and understand the heat convection paths in the 3D IC package. The results reveal these phenomena of the complete structure, including TSV and bump, and highlight the different thermal conductivities of the materials used in creating the 3D IC packages.

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