Zhi‐Yuan Cui, Yeong‐Seuk Kim, Moon‐Ho Choi, Hyung‐Gyoo Lee and Nam‐Soo Kim
The purpose of this paper is to present the design and optimization of a comparator with two transistors.
Abstract
Purpose
The purpose of this paper is to present the design and optimization of a comparator with two transistors.
Design/methodology/approach
The effect of back‐gate bias in MOSFET is analyzed and applied to a comparator circuit in a flash‐type A/D converter (ADC). The 4‐bit flash ADC is simply structured by change of comparator block based on CMOS latch with pMOSFET switch. The back‐gate bias on MOSFET changes the threshold voltage and provides for a CMOS inverter to shift the voltage transfer characteristics. In the new type comparator, the variation of turn‐on voltage is controlled within 0.1 V in 4‐bit ADC. The fabrication is done in a 0.35 μm single‐poly four‐metal process.
Findings
Layout simulation shows that INL is within 0.3 LSB and SNDR is 25.4 dB at input frequency of 20 KHz and sampling rate of 4 MS/s. The 0.26 × 0.43 mm 2 ADC dissipates 1.2 mW at supply voltage of 3.3 V.
Originality/value
A comparator which uses the effect of the back‐gate bias on MOSFET is applied to a flash ADC. The paper is of value in showing how the circuit of this comparator is quite simple compared with a conventional comparator based on a CMOS latch, which is adaptable for a low‐power analog circuit in future. The experimental output of the 4‐bit flash ADC shows a good agreement with a simulation. Power consumption 1.2 mW, INL 0.2 LSB, and SNDR 25 dB are obtained in the simulation study.