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Thermal cycling tests and failure modelling were conducted on FR‐4 and cyanate ester printed circuit board (PCB) substrate materials to evaluate reliability limits tor solder and repair processes, particularly for high pin count, through‐ hole devices. The boards used were double‐sided, 0.125 in. thick with 0.029 in. diameter plated‐through holes (PTHs). Thermal cycling was accomplished using hot oil immersion at 240°C and 260°C followed by forced room‐temperature air. The average number of thermal cycles‐to‐failure was 10 for FR‐4, 20 for cyanate ester epoxy blend, and 50 for cyanate ester. Weibull statistics were used to predict failure rates for various pin count devices. Failure analysis was used to identify the mechanism of failure, and modelling was used to predict cycles‐to‐failure based on typical material properties. The primary failure mechanism was corner cracking in FR‐4 and a combination of corner cracking and barrel cracking in the cyanate ester materials. The modelling used a modified pad tilt geometry combined with Coffin‐Manson low cycle fatigue theory, which resulted in predictions of the same order as those for the cycling tests. Key material properties and process parameters were identified that controlled the failure response of the plated‐through hole and board substrate combinations.

Dr. Lajos Kovacs, president of the varnish and paint section of the Hungarian Chemical Society and current president of FATIPEC is to retire owing to ill‐health, from his position as technical director of Buddalakk Paint and Synthetic Resin Works. Dr. Kovacs has been active in the varnish and paint industry for 35 years, 20 of which he has spent in his present position.