Search results

The encapsulation of electronic assemblies within thermoplastic polymers is an attractive technology for the protection of circuitry used in harsh environments, such as those experienced in automotive applications. However, the relatively low‐thermal conductivity of the encapsulating polymer will introduce a thermally insulating barrier, which will impact on the dissipation of heat from the components and may result in the build‐up of stresses in the structure. This paper therefore seeks to present the results from computational models used to investigate the thermal and thermo‐mechanical issues arising during the operation of such electronic modules. In particular, a two‐shot overmoulded structure comprising an inner layer of water soluble and an outer layer of conventional engineering thermoplastics was investigated, due to this type of structure's potential to enable the easy separation of the electronics from the polymer at the end‐of‐life for recycling.

Representative finite element models of the overmoulded electronic structures were constructed and the effects of the polymer overmould were analysed through thermal and thermo‐mechanical simulations. Investigations were also carried out to explore the effect of materials properties on the overmoulded structure.

Models have shown that some power de‐rating of components is required to prevent temperatures exceeding those in unencapsulated circuits and have quantified the benefits of adding thermally conductive fillers to the polymer. Simulations have also clearly demonstrated the benefits of foamed polymers in reducing thermal stresses in the assemblies, despite their poorer thermal conductivity compared with solid polymers.

The paper illustrates the thermal issues affecting the overmoulded electronics and gives some guidelines for improving their performance.

Increases in component packing density and the consequent decrease in feature size in electronics products continue to place ever more emphasis on process design to manage or predict the outcome of the inherent process/materials interactions. The most significant pressure is for improved first‐off process yields because of high cost and technical difficulty of rework processes and concerns about the life of reworked products. The current dominant process for the production of surface mount assemblies is the reflow soldering of stencil printed solder paste. This paper presents the results of work that begins to describe the sub‐processes of solder paste reflow. It is essential to understand and optimise these complex physical processes when aiming for the six‐sigma level quality demands of electronics manufacture.

The final geometry of the solder joints in surface mount technology (SMT) assemblies is dependant upon the design rules, the materials and the manufacturing processes used. An understanding of these dependencies should allow the design of assemblies that have satisfactory thermal fatigue strength, while minimising the probability of process defects such as shorts and opens. This paper presents preliminary results from the use of a computational modelling tool, the Surface Evolver, in the simulation of the formation and geometry of solder joints and in the understanding of solder wetting phenomena. The paper also identifies other application areas for Evolver relevant to SMT.

Previous models of temperature development during the reflow soldering process have typically used commercially available, general purpose, finite difference/finite element modelling tools to create detailed three dimensional representations of both the product and of the reflow furnace. Such models have been shown to achieve a high degree of accuracy in predicting the temperatures a particular PCB design will achieve during the reflow process, but are complex to generate and analysis times are long, even when using modern high performance computer workstations.This paper will report on the development of a simplified model of the process, which uses less complex representations of both the product and the process, together with a simple numerical solver developed specifically for this application, whilst achieving an accuracy comparable with more detailed models. In the simplified model, the product is divided into elements, which are represented using a two‐dimensional mesh of thermal conductances linking thermal masses. The values of these conductances and masses are calculated based on the averaged properties of the PCB material and attached components within the area of each of the elements. The representation of the specific reflow furnace is based on measurements of the temperature and level of thermal convection at each point along the length of the furnace, thereby avoiding the necessity of making detailed measurements of the furnace geometry and air flow velocities. The combination of these two simplification techniques allow the reduction of analysis time for a relatively simple PCB from in the order of an hour on a high performance Unix workstation to under a second on a Pentium class PC running Microsoft Windows.

Reflow soldering process is an important step of the surface mount technology. The purpose of this paper is to minimize the maximum warpage of shielding frame by controlling reflow soldering control parameters.

Compared with other reflow-related design methods, both time and temperate of each extracted time region are considered. Therefore, the number of design variable is increased. To solve the high-dimensional problem, a surrogate-assisted optimization (SAO) called adaptive Kriging high-dimensional representation model (HDMR) is used.

Therefore, the number of design variable is increased. To solve the high-dimensional problem, a surrogate-assisted optimization (SAO) called HDMR is used. The warpage of shield frame is significantly reduced. Moreover, the correlations of design variables are also disclosed.

Compared with the original Kriging HDMR, the expected improvement (EI) criterion is used and a new projection strategy is suggested to improve the efficiency of optimization method. The application suggests that the adaptive Kriging HDMR has potential capability to solve such complicated engineering problems.

A neural‐network‐based predictive model is proposed to model the second‐side thermal profile reflow process in surface mount assembly with a view to facilitating the oven set‐up procedure and improving production yield.

This study performs a 3⁸⁻⁴ fractional factorial experimental twice to collect the thermal‐profile data from a second‐side board. The first experiment has components on the second side only, while the second experiment also has additional components on the primary side. A back‐propagation neural network (BPN) is then used to model the relationship between control variables and thermal‐profile measures.

Empirical results illustrate the efficiency and effectiveness of the proposed BPN in solving the second‐side thermal‐profile prediction and control problem.

There is no study dedicated to the investigation of the second‐side thermal‐profile variance with and without the presence of primary‐side components. The study suggests that a variant oven‐setting strategy for the second‐side reflow process is important to ensure reflow‐soldering quality.

This paper describes a technique for the monitoring and control of the reflow soldering process. The technique combines state‐of‐the‐art infra‐red (IR) sensor technology, coupled with application‐specific process monitoring and control software, providing a unique capability both to monitor product temperatures during processing and to modify the process settings. The development of techniques to allow variation of the heat transfer from the oven to the in‐process printed circuit assemblies (PCAs) provides the means to adjust the soldering oven’s process settings for each individual PCA. This automatic profiling ensures consistent thermal histories and optimises oven energy consumption. Archiving of the reflow profiles along with temperatures recorded for each PCA provides full traceability to the reflow process settings for each individual PCA. The incorporation of IR sensing technology also provides a means to monitor the performance of the process.

Because of new requirements related to the employment of lead‐free manufacturing and the diversity of components and metal finishes on high density printed circuit boards, better understanding and control of the reflow process is required in order to achieve acceptable yields and reliability of SMT assemblies. Accurate control of the temperature distributions within components and boards during the reflow process is one of the major requirements, especially in lead‐free assembly. This paper outlines a scheme for reflow modelling and presents an oven‐level model of the steady state flow‐field inside a reflow oven, which will be needed in subsequent transient analysis and small‐scale modelling. The model is constructed by utilising the advanced computational fluid dynamics (CFD) technology using commercial software. The computational results are discussed and compared with measured data.

The simulated temperature profile of the printed circuit board assembly (PCBA) during reflow soldering process deviates from the actual profile. To reduce this relative deviation, a new strategy based on the Kriging response surface and the Multi-Objective Genetic Algorithm (MOGA) optimizing method is proposed.

The simulated temperature profile of the PCBA during reflow soldering process deviates from the actual profile. To reduce this relative deviation, a new strategy based on the Kriging response surface and the MOGA optimizing method is proposed.

Several critical influencing parameters such as temperature and the convective heat transfer coefficient of the specific temperature zones are selected as the correction parameters. The hyper Latins sampling method is implemented to distribute the design points, and the Kriging response surface model of the soldering process is constructed. The updated model is achieved and validated by the test. The relative derivation is reduced from the initial value of 43.4%–11.8% in terms of the time above the liquidus line.

A new strategy based on the Kriging response surface and the MOGA optimizing method is proposed.

The embedding of passive components such as resistors, capacitors and inductors within printed circuit boards (PCBs) is motivated, to a large extent, by the desire for increased miniaturisation of electronic goods. However, resistors and, to a lesser extent, inductors are heat generating devices, and the temperature developed within PCBs as the result of the operation of embedded passives is a significant aspect of the design of a multilayer PCB. Here we investigate, by simulation, temperature fields associated with operation of embedded resistors. It is shown that for board dimensions less than 2cm × 2cm temperatures achieved are higher than those associated with larger boards having identical structures and identical resistor heat generation. Detailed simulations are used to investigate the sensitivity of the temperature rises associated with embedded resistors to copper track coverage and to thermal coupling of the PCB to ambient on its upper and lower surfaces. The implications of these findings are discussed both in the context of the design of real PCBs and in the context of thermal simulation.