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With decreasing vertical dimensions of the bipolar transistor (BJT), non‐local effects of nonuniform electron temperature should have a significant effect on the BJT characteristics. These effects can be simulated using a hydrodynamic (HD) model of the BJT, in which the equation of energy balance is added to the set of Poisson's and continuity equations.

A general algorithm for analysis of semiconductors with arbitrary models for heavy doping phenomena is presented. Different models, theoretical as well as empirical, were applied, and minority carrier concentration in the uncompensated n‐type silicon was analyzed. Recalculated into the term of apparent BGN, the results were compared with experimental data. Further analysis of apparent BGN indicated the weakness of empirical formulae for apparent BGN. Assumption of total ionization of impurities considered in the analysis is discussed and justified.

The main purpose of this paper is to find a simple method to improve the breakdown voltage of BJTs fabricated on SOI.

We have used two‐dimensional device simulation to examine the effect of a collector tub on the collector breakdown of the SOI based BJTs. This method involves creating a collector tub by etching the buried oxide followed by an n‐type implantation on the collector n/n+ junction side.

First, our method reduces the peak electric field at the silicon film‐BOX interface and secondly, the collector‐tub facilitates the collector potential to be absorbed by both collector drift and substrate regions improving the collector breakdown significantly.

An improved breakdown voltage improves the reliability of BJTs on SOI.

Our results show that the BV_CEO of the bipolar transistors with a collector‐tub is enhanced by 2.7 times when compared with a conventional lateral bipolar transistor (LBT) with identical drift region doping. This improvement has an important practical value in the fabrication of SOI‐based LBTs.

Analysis of piecewise linear resistive networks, described by nodal equations, using the Gauss‐Seidel method is presented in the paper. The conditions which guarantee the existence of a unique solution and convergence of the iterative technique are formulated. An algorithm is described and a numerical example is demonstrated.

A numerical implementation of a discretization scheme of the hydrodynamic model for submicron devices is described and applied to a one‐dimensional ballistic diode. The performance of the numerical method and the physical results of the simulation for different biases and lattice temperatures, and a brief comparison to Monte Carlo simulations, are also given.

Time and frequency domain complementary numerical models of microwave non‐linear circuits using two‐terminal active semiconductor devices are presented. Their main feature is the use of numerical one‐dimensional macroscopic physical models as semiconductor device models. Their respective capability is illustrated by some results of a study devoted to the optimization of millimeter‐wave avalanche diode frequency multipliers.

The effects of polysilicon emitter on the high frequency performance of bipolar transistors have been investigated numerically. The presence of polysilicon grain boundaries was found to slow down the response of the device. This resulted in a lower fT for polysilicon emitter bipolar transistors with a clean polysilicon/ mono‐crystalline silicon interface compared to conventional transistors with an identical emitter‐base junction depth. The interfacial oxide layer that could exist at the polysilicon/mono‐crystalline silicon interface can, depending on the relative thickness of the polysilicon and mono‐crystalline silicon emitter regions, either improve or deteriorate the high frequency performance of the device. For a mono‐crystalline silicon emitter region that is much thinner than the polysilicon emitter region, the lower the tunnelling probability of the interfacial oxide layer the better is the improvement in fT. However, if the thickness of the mono‐crystalline silicon emitter region is made larger with respect to the polysilicon emitter region, the converse can be true.

The present paper discusses the development of a test methodology for evaluation of the electrical performance of flip‐chip devices. A dedicated test chip was designed for this experiment. The test structure contains passive and active semiconductor devices manufactured using CMOS technology. Bond pads were designed to facilitate bumping. A Printed Circuit Board (PCB) housing the flipped devices was also designed for easy access to the individual devices. A test set‐up for measuring the structures was developed and key device parameters to monitor the electrical performance of the structures were identified.The results show that the proposed test structure is a suitable tool for determining the electrical parameters of flip‐chip devices. The experimental set‐up is universal and can be adapted to suit different custom‐designed flip‐chip test structures. In addition, the developed test set‐up is computer controlled and allows easy adaptation to different measurement techniques and devices.

To use the 4H-SiC material in integrated circuits for high temperature application, an accurate and simple circuit model of n-channel planar 4H-SiC MOSFET is required.

In this paper, a SPICE model of n-channel planar 4H-SiC MOSFET was built based on the device simulation results and measurement results. Firstly, a device model was simulated with Sentaurus TCAD, with measured parameters from fabricated planar 4H-SiC MOSFET previously. Then the device simulation results were analyzed and parameters for SPICE models were extracted. With these parameters, an accurate SPICE model was built and simulated.

The SPICE model exhibits the same performance as the measured results with different environment temperatures. The simulation results indicate that the maximum fitting error is 0.22 mA (7.33% approximately) at 200 °C. A common-source amplifier with this model is also simulated and the simulated gain is stable at different environment temperatures.

This paper provides a reliable modeling method for n-Channel Planar 4H-SiC MOSFET and reference value for the design of 4H-SiC high temperature integrated circuit.

Research reveals very little about how the supervision of social studies student teachers ought to be enacted. The paper aims to discuss this issue.

Based on the broader arguments for the democratic purposes of social studies, the author argues for the development of the democratic capacities of teacher citizens by creating deliberative and dialogic spaces in social studies field-based teacher education.

Four conceptual dimensions of dialogic pedagogy in the supervision of social studies student teachers are explored: questioning, listening, negotiation, and self-critique.

Because supervision of student teachers is a pedagogical interaction, a pedagogy of social studies field-based teacher education must be grounded in dialogue and deliberation.