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Attempts to define competitive advantage within an industry. Identifies the need for a competitive strategy specific to the enterprise and industry concerned. Considers the structure of the industry, the scope of profitability and positioning of the company. Looks at competitive advantage within global industries in relation to global strategy, early reactions and alliances. Suggests the winners will need to be progressive, innovative, quality firms which continue to react quickly to new developments, take risks and invest.

The purpose of this paper is to measure and analyze industry export competitiveness of India and it tries to achieve this by presenting a multi‐dimensional framework for measuring and illustrating industry export competitiveness.

The framework considers industry specialization, industry export growth rate, and relative export market share for a dataset of 97 different Indian industries over a five year period (2001‐2005).

The analyses identifies four different types of industry groups, namely domestic static, domestic dynamic, global dynamic and global static. The result shows that the majority of Indian industries are dynamic and growing faster than the world export growth rate for the period of study. A total of 40 percent of India's industries are more global, in terms of industry specialization, compared to the world average, with such highly specialized industries as silk, gums, carpets and textiles, floor coverings, pearls, precious stones and metals. The authors show that industry specialization leads to dominance in worldwide export market share. India's global dynamic industries are mainly in the raw materials, commodities and skilled manual labor rather than high tech or manufacturing sectors.

The framework allows us to measure and illustrate industry export competitiveness and permits an intra‐country comparison, a comparison of various industries of one country, or permits an inter‐country comparison, a comparison of one industry across different countries.

The framework should help policymakers, government officials, industry associations, and company executives to assess their export competitiveness and focus on protecting or promoting certain industries by directing scarce resources to sectors where they may count the most. The findings of the study can also be useful for international bodies such as UNCTAD and world‐bank in identifying regional industry that can foster growth of trade and economies in the South‐Asian region.

The framework used is conceptually innovative and applicable to a variety of contexts for modeling industry export competitiveness. The framework also facilitates inter‐ and intra‐country export benchmark analyses.

The purpose of this paper is to focus on through‐silicon via (TSV), with a new concept that every chip or interposer could have two surfaces with circuits. Emphasis is placed on the 3D IC integration, especially the interposer (both active and passive) technologies and their roadmaps. The origin of 3D integration is also briefly presented.

This design addresses the electronic packaging of 3D IC integration with a passive TSV interposer for high‐power, high‐performance, high pin‐count, ultra fine‐pitch, small real‐estate, and low‐cost applications. To achieve this, the design uses chip‐to‐chip interconnections through a passive TSV interposer in a 3D IC integration system‐in‐package (SiP) format with excellent thermal management.

A generic, low‐cost and thermal‐enhanced 3D IC integration SiP with a passive interposer has been proposed for high‐performance applications. Also, the origin of 3D integration and the overview and outlook of 3D Si integration and 3D IC integration have been presented and discussed. Some important results and recommendations are summarized: the TSV/redistribution layer (RDL)/integrated passive devices passive interposer, which supports the high‐power chips on top and low‐power chips at its bottom, is the gut and workhorse of the current 3D IC integration design; with the passive interposer, it is not necessary to “dig” holes on the active chips. In fact, try to avoid making TSVs in the active chips; the passive interposer provides flexible coupling for whatever chips are available and/or necessary, and enhances the functionality and possibly the routings (shorter); with the passive interposer, the TSV manufacturing cost is lower because the requirement of TSV manufacturing yield is too high (>99.99 percent) for the active chips to bear additional costs due to TSV manufacturing yield loss; with the passive interposer, wafer thinning and thin‐wafer handling costs (for the interposer) are lower because these are not needed for the active chips and thus adds no cost due to yield loss; with the current designs, all the chips are bare; the packaging cost for individual chips is eliminated; more than 90 percent of heat from the 3D IC integration SiP is dissipated from the backside of high‐power chips using a thermal interface material and heat spreader/sink; the appearance and footprint of current 3D IC integration SiP designs are very attractive to integrated device manufactures, original equipment manufactures, and electronics manufacturing services (EMS) because they are standard packages; and underfills between the copper‐filled TSV interposer and the high‐ and low‐power chips are recommended to reduce creep damage of the lead‐free microbump solder joints and prolong their lives.

The paper's findings will be very useful to the electronic industry.

This paper aims to investigate the factor analysis for balanced scorecard (BSC) as measuring competitive advantage of infrastructure assets of owned state ports in Indonesia: Pelindo IV, Makassar, Indonesia.

This investigation adopts an explanatory and an exploratory qualitative case study method to analyze the effectiveness of BSC over the strategy management processes. For data collection, the researchers have used semi-structured interviews, direct observation and document collection. Data collection was made during a six-month period, which allowed gaining of deep knowledge on the culture and management methods used in alpha. Other data collected refer to the company’s documentation and reporting of online media publications. Detailed interview data are the main data sources, which allow obtaining of a detailed and holistic understanding of the experience, opinions and attitudes of the interviewees. Interviews focus on asset management to determine the relationship between various factors. This study adopts ideal BSC principle (four perspectives) to develop strategic map for infrastructure asset of Pelindo IV. Analysis tools using factor analysis for the indicators (financial, customer, learning-growth and internal process) measure the competitive advantages. The data for factor analysis from the perception of each stakeholder using questionnaire are collected.

The competitive advantages of Pelindo IV depend on 81.2 per cent from financial perspective, customer perspective, internal process perspective and learning perspective, and 18.2 per cent from the other factor. The result of measurement model of competitive advantage in Figure 2 is significantly (p-value < 0.05) measured by financial perspective performance, customer perspective performance, internal process perspective performance and learning perspective performance. On the basis of the highest coefficient loading factor, it can be shown that the most powerful competitive advantages are measured by learning perspective. The high value of competitive advantage of Pelindo IV, Makassar, Indonesia, is especially seen from the learning perspective performance. The order result of BSC for measuring the competitive advantages is as follows: learning perspective performance, financial perspective performance, customer perspective performance and internal process perspective performance.

Originality of this study looks at the following three points: first, the measurement competitive advantages. Previous studies used measurements of cost leadership strategy, differential strategy and focus strategy as competitive advantages measuring (Porter, 1985; Warf and Stutz, 2007; Clulow et al., 2003). This study uses BSCs with four indicators (financial perspective result, customer perspective result, internal process perspective result and learning perspective). Second, on the other hand, several studies have investigated the BSCs as performance measurement (Ozturk and Coskun, 2014; Malgwi and Dahiru, 2014; Binden et al., 2014). Third, this study uses the factor analysis to measure the competitive advantage by BSCs, which is different from the previous study analysis.

The purpose of this paper is to review recent advances in wire bonding of low‐k devices.

Dozens of journal and conference articles published in 2005‐2008 are reviewed.

The paper finds that many articles have discussed and analysed problems/challenges such as bond pad metal peeling/lift, non‐sticking on pad, decreased bonding strength and lower wire‐bond assembly yield. The paper discusses the articles' solutions to the problems and recent findings/developments in wire bonding of low‐k devices.

Because of the page limitation, only brief discussions are given in this paper. Further reading is needed for more details.

The paper attempts to provide an introduction to recent developments and the trends in wire bonding of low‐k devices. With the references provided, readers may explore more deeply by reading the original articles.

This paper seeks to review recent advances in wire bonding, flip chip and lead‐free solder for advanced microelectronics packaging.

Of the 91 journal papers, 59 were published in 2005‐2007 and topics related to wire bonding, flip chip and lead‐free solder for advanced microelectronics packaging are reviewed.

Research on advanced wire bonding is continuously performed for advanced and complex applications such as stacked‐dies wire bonding, wire bonding of low‐k ultra‐fine‐pitch devices, and copper wire bonding. Owing to its many advantages, flip chip using adhesive has gained more popularity. Research on the reliability of lead‐free solder joints is being conducted world‐wide. The new challenges, solutions and new developments are discussed in this paper.

Because of page limitation of this review paper and the large number of the journal papers available, only a brief review is conducted. Further reading is needed for more details.

This review paper attempts to provide introduction to recent developments and the trends in terms of the topics for advanced microelectronics packaging. With the references provided, readers may explore more deeply, focusing on a particular issue.

The purpose of this paper is to review recent advances in fine and ultra‐fine pitch wire bonding.

Dozens of journal and conference articles published recently are reviewed.

The problems/challenges such as possible wire sweep and decreased bonding strength due to small wire sizes, non‐sticking, metal pad peeling, narrow process windows, wire open and short tail defects are analysed. The solutions to the problems and recent findings/developments in fine and ultra‐fine pitch wire bonding are discussed.

Because of the page limitation, only brief discussions are given in this paper. Further reading is needed for more details.

This paper attempts to provide an introduction to recent developments and the trends in fine and ultra‐fine pitch wire bonding. With the references provided, readers may explore more deeply by reading the original articles.

This paper attempts to review recent advances in wire bonding using insulated wire and new challenges in wire bonding for advanced microelectronics packaging.

Dozens of journal articles, conference articles and patents published or issued in 2004‐2007 are reviewed.

The advantages and problems/challenges related to wire bonding using insulated wire are briefly analysed, and several solutions to the problems and recent findings/developments related to wire bonding using insulated wire are discussed.

Because of page limitation of the paper, only brief review is conducted. Further reading is needed for more details.

This paper attempts to provide introduction to recent developments and the trends in wire bonding using insulated wire. With the references provided, readers may explore more deeply by reading the original articles and patent documents.