Search results

The purpose of this study is to use the Taguchi Method for parametric design in the early stages of product development. electromagnetic compatibility (EMC) issues can be considered in the early stages of product design to reduce counter-measure components, product cost and labor consumption increases due to a number of design changes in the R&D cycle and to accelerate the R&D process.

The three EMC characteristics, including radiated emission, conducted emission and fast transient impulse immunity of power, are considered response values; control factors are determined with respect to the relevant parameters for printed circuit board and mechanical design of the product and peripheral devices used in conjunction with the product are considered as noise factors. The optimal parameter set is determined by using the principal component gray relational analysis in conjunction with both response surface methodology and artificial neural network.

Market specifications and cost of components are considered to propose an optimal parameter design set with the number of grounded screw holes being 14, the size of the shell heat dissipation holes being 3 mm and the arrangement angle of shell heat dissipation holes being 45 degrees, to dispose of 390 O filters on the noise source.

The optimal parameter set can improve EMC effectively to accommodate the design specifications required by customers and pass test regulations.

This paper aims to consider the practical production environment of electronics manufacturing industry firms, and the large quantities of information collected on machine processes, testing data and production reports, while simultaneously taking into account the properties of the processing environment, in conducting analysis to obtain valuable information.

This research constructs a prediction model of the circuit board assembly process yield. A decision tree is used to extract the key attributes. The authors also integrate association rules to determine the relevance of key attributes of undesirable phenomena.

The results assure the successful application of the methodology by reconfirming the rules for solder skip and short circuit occurrence and their causes.

Measures for improvement are recommended, production parameters determined and debugging suggestions made to improve the process yield when the new process is implemented.

This paper aims to propose an innovative parametric design for artificial neural network (ANN) modeling for the multi-quality function problem to determine the optimal process scenarios.

The innovative hybrid algorithm gray relational analysis (GRA)-ANN and the GRA-Entropy are proposed to effectively solve the multi-response optimization problem.

Both the GRA-ANN and the GRA-Entropy analytical approaches find that the optimal process scenario is a stencil aperture of 57 per cent and immediate processing of the printed circuit board after exposure to a room environment.

A six-week confirmation test indicates that the optimal process has improved quad flat non-lead assembly yield from 99.12 to 99.78 per cent.

This research aims to study the stencil printing process of the quad flat package (QFP) component with a pin pitch of 0.4 mm. After the optimization of the printing process, the desired inspection specification is determined to reduce the expected total process loss.

Static Taguchi parametric design is applied while considering the noise factors possibly affecting the printing quality in the production environment. The Taguchi quality loss function model is then proposed to evaluate the two types of inspection strategies.

The optimal parameter-level treatment for the solder paste printing process includes a squeegee pressure of 11 kg, a stencil snap-off of 0.14 mm, a cleaning frequency of the stencil once per printing and using an air gun after stencil wiping. The optimal upper and lower specification limits are 119.8 µm and 110.3 µm, respectively.

Noise factors in the production environment are considered to determine the optimal printing process. For specific components, the specification is established as a basis for subsequent processes or reworks.

This study aims to focus on the passive components of System in Package SiP modules and discusses the geometric pad designs for 01005-sized passive components, the front end design of the hole size and shape of the stencil and the parameters of the stencil sidewall coating, to determine the optimum parameter combination.

This study plans and conducts experiments, where a L8(27) inner orthogonal array is built to consider the control factors, including a L4(23) outer orthogonal array to consider the noise factor, and the experimental data are analyzed by using the technique for order preference by similarity to ideal solution multi-quality analysis method.

The results show that the optimum design parameter level combination is that the solder mask opening pad has no solder mask in the lower part of the component, the pad width is 1.1 times that of the component width, the pad length is 1.75 times that of the electrode tip length, the pad spacing is 5 mil, the stencil open area is 90% of the pad area, the stencil opening corner has a 3 mil chamfer angle, and the stencil sidewall is free of nano-coating.

The parameter design and multi-quality analysis method, as proposed in this study, can effectively develop the layout of passive components on a high-density SiP module substrate, to stabilize the process and increase the production yield.

This paper aims to discuss the key factors affecting the quality characteristics, such as the number of solder balls, the spread distance of residual underfill and the completion time of the underfilling.

The Taguchi method is applied to configure the orthogonal table and schedule and execute the experiment. In addition, principal components analysis is used to obtain the points. Then, based on gray relational analysis and the technique for order preference by similarity to ideal solution, the closeness between each quality characteristic and the ideal solution is adopted as the basis for evaluating the quality characteristics.

The optimal parameter combination is proposed, which includes 4 dispensing (11 mg/dispensing), a “half flow” interval state, 80°C preheating module PCB board and an L-shaped dispensing path and verification testing is performed.

For vehicles and handheld electronic products, solder joints that connect electronic components to printed circuit boards may be cracked due to collision, vibration or falling. Consequently, solder balls are closely surrounded and protected by the underfill to improve joint strength and resist external force factors, such as collision and vibration. This paper addresses the defects caused during the second reflow process of a vehicle electronic communication module after the underfilling process.

Differing from previous studies trying to solve the electromagnetic compatibility (EMC) issue by addressing single factor, this study aims to combine measures of shielding, filtering and grounding to design parameters with the Taguchi method at the beginning of product design to come up with the optimal parameter combination.

EMC-related performance such as radiated emission, conduction interference and electrical fast transient/burst immunity (EFT) are response variables, whereas the printed circuit board and mechanic design-relevant parameters are considered as control factors. The noise factors are peripherals used together with the tablet.

The optimal design parameter matrix based on results from the application and integration of multivariate analysis method of principal component grey relation and technique for order preference by similarity to ideal solution suggests 14 grounding screw holes, cooling aperture of casing at diameter of 3 mm and staggered layout and 300O filter located at source of noise. Validation of this matrix shows around 10, 1 and 8 per cent improvement in radiation, conduction interference and EFT immunity.

The multivariate quality parameters’ design method proposed by this study improves EMC characteristics of products and meets the design specification required by customer, accelerating electronic product research and development process and complying with electromagnetic interference test regulations set forth by individual country.

The purpose of this paper is to comprehensively explore the effects of critical parameters on solder deposition and to establish a systematic approach for determining guidelines for solder paste inspection (SPI) workstations.

This study explored the effects of process parameters, stencil and printed circuit board designs on solder deposition and identified the major post‐reflow defect scenarios. Through the investigation of correlation between the results of SPI analysis and post‐reflow defective scenarios, SPI specifications are suggested for minimizing the total cost of poor quality.

The higher the printing pressure the lower the solder deposition. There was a significant difference in solder deposition between the front squeegee and the rear squeegee. Insufficient distance between the stencil aperture and the initial printing location resulted in irregular solder paste and variations in solder deposition. A stencil with a higher area ratio resulted in greater solder deposition and less variation. Stencil apertures parallel to the direction of printing were superior to a 45° vector print. Further, the nominal solder thickness should take into account the thicknesses of the solder mask and the legend ink. There was an offset in the results of SPI measurements between the solder mask defined (SMD) pads and non‐SMD pads. The specifications for solder deposition with irregular stencil apertures need to be adjusted.

To address the arbitrariness of existing industry practice, this study was a joint effort with a Taiwan‐based electronics manufacturing service company. Real data were taken from a mass production environment and inferences were then made based on a statistical analysis.

The purpose of this paper is to employ data mining as a new diagnosing scheme for investigating void formation to the thermal pad in quad flat non‐lead (QFN) assembly. Occurrences of voiding in various scenarios of component design, materials selection and manufacturing process are analyzed.

This research investigates the process yield of a PCB assembly for a handheld device in the electronics manufacturing industry using the chi‐square automatic interaction detection (CHAID) algorithm and chi‐square test. Practical data generated by an X‐ray apparatus from the shop floor are collected. The critical attributes to the void formation (in the solder joint) of the QFN component are identified.

Stocking the PCB material beyond ten days may increase the level of voiding by 1%. Using PCB provided by vendor U helps decrease the level of voiding by 1.6%. Stocking the component material above 43 days may increase the level of voiding by 1.9%. In addition, reflow soldering profile with time above liquid (TAL) less than or equal to 62 sec and with peak temperature higher than or equal to 241°C generate less voids. Finally, the via‐in‐pad design causes a concave geometry on the surface of thermal pad which contributes to the voiding formation. The amount of voiding can be further diminished by plugging the via with plated copper.

This research implements CHAID that extracts useful knowledge from a huge amount of manufacturing data in order to realize the complex interaction effects through automated analysis. The extent of voiding in the samples using the optimal process suggested through CHAID algorithm can be reduced from 16% to 10.2%.

The purpose of this paper is to investigate how to reduce the time and cost required to conduct reliability testing. With increasing competition in the electronics industry and reduction in product life cycles, it is essential to diminish the time required for new product development and thus time to market.

This study conducts empirical sample test for wireless card and analyzes the fatigue life through finite element modeling (FEM). Simulation results are compared to the data collected from a temperature cycling test under conditions of −40°C to 150°C and −40°C to 100°C.

Assuming that the results of product lifetime from empirical sample test and software simulation exhibit a linear relationship, a “scale factor” should exist for any given product structure, process condition and materials composition scenario. The scale factors were found to be approximately 0.1 in both temperature cycling scenarios. Also, the effectiveness of various adhesive dispensing patterns on solder joint reliability is evaluated through software simulation. The L shape adhesive dispensing was proven to effectively enhance the fatigue life of chip scale package solder joints roughly 100‐fold.

The scale factor is used to convert the results from software simulation to empirical sample test for a given set of processing environments and materials. This helps to reduce the time and cost required to conduct reliability testing.