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The purpose of this paper is to introduce new implementations for parallel processing applications using bijective systolic networks and their corresponding carbon-based field emission controlled switching. The developed implementations are performed in the reversible domain to perform the required bijective parallel computing, where the implementations for parallel computations that utilize the presented field-emission controlled switching and their corresponding many-valued (m-ary) extensions for the use in nano systolic networks are introduced. The second part of the paper introduces the implementation of systolic computing using two-to-one controlled switching via carbon-based field emission that were presented in the first part of the paper, and the computational extension to the general case of many-valued (m-ary) systolic networks utilizing many-to-one carbon-based field emission is also introduced.

The introduced systolic systems utilize recent findings in field emission and nano applications to implement the functionality of the basic bijective systolic network. This includes many-valued systolic computing via field-emission techniques using carbon-based nanotubes and nanotips. The realization of bijective logic circuits in current and emerging technologies can be very important for various reasons. The reduction of power consumption is a major requirement for the circuit design in future technologies, and thus, the new nano systolic circuits can play an important role in the design of circuits that consume minimal power for future applications such as in low-power signal processing. In addition, the implemented bijective systems can be utilized to implement massive parallel processing and thus obtaining very high processing performance, where the implementation will also utilize the significant size reduction within the nano domain. The extensions of implementations to field emission-based many-valued systolic networks using the introduced bijective nano systolic architectures are also presented.

Novel bijective systolic architectures using nano-based field emission implementations are introduced in this paper, and the implementation using the general scheme of many-valued computing is presented. The carbon-based field emission implementation of nano systolic networks is also introduced. This is accomplished using the introduced field-emission carbon-based devices, where field emission from carbon nanotubes and nano-apex carbon fibers is utilized. The implementations of the many-valued bijective systolic networks utilizing the introduced nano-based architectures are also presented.

The introduced bijective systolic implementations form new important directions in the systolic realizations using the newly emerging nano-based technologies. The 2-to-1 multiplexer is a basic building block in “switch logic,” where in switch logic, a logic circuit is realized as a combination of switches rather than a combination of logic gates as in the gate logic, which proves to be less costly in synthesizing multiplexer-based wide variety of modern circuits and systems since nano implementations exist in very compact space where carbon-based devices switch reliably using much less power than silicon-based devices. The introduced implementations for nano systolic computation are new and interesting for the design in future nanotechnologies that require optimal design specifications of minimum power consumption and minimum size layout such as in low-power control of autonomous robots and in the adiabatic low-power VLSI circuit design for signal processing applications.

The introduced bijective systolic implementations form new important directions in the systolic realizations utilizing the newly emerging nanotechnologies. The introduced implementations for nano systolic computation are new and interesting for the design in future nanotechnologies that require optimal design specifications of high performance, minimum power and minimum size.

The purpose of this paper is to introduce an approach for m‐valued classical and non‐classical (reversible and quantum) optical computing. The developed approach utilizes new multiplexer‐based optical devices and circuits within switch logic to perform the required optical computing. The implementation of the new optical devices and circuits in the optical regular logic synthesis using new lattice and systolic architectures is introduced, and the extensions to quantum optical computing are also presented.

The new linear optical circuits and systems utilize coherent light beams to perform the functionality of the basic logic multiplexer. The 2‐to‐1 multiplexer is a basic building block in switch logic, where in switch logic a logic circuit is implemented as a combination of switches rather than a combination of logic gates as in the gate logic, which proves to be less‐costly in synthesizing wide variety of logic circuits and systems. The extensions to quantum optical computing using photon spins and the collision of Manakov solitons are also presented.

New circuits for the optical realizations of m‐valued classical and reversible logic functions are introduced. Optical computing extensions to linear quantum computing using photon spins and nonlinear quantum computing using Manakov solitons are also presented. Three new multiplexer‐based linear optical devices are introduced that utilize the properties of frequency, polarization and incident angle that are associated with any light‐matter interaction. The hierarchical implementation of the new optical primitives is used to synthesize regular optical reversible circuits such as the m‐valued regular optical reversible lattice and systolic circuits. The concept of parallel optical processing of an array of input laser beams using the new multiplexer‐based optical devices is also introduced. The design of regular quantum optical systems using regular quantum lattice and systolic circuits is introduced. New graph‐based quantum optical representations using various types of quantum decision trees are also presented to efficiently represent quantum optical circuits and systems.

The introduced methods for classical and non‐classical (reversible and quantum) optical regular circuits and systems are new and interesting for the design of several future technologies that require optimal design specifications such as super‐high speed, minimum power consumption and minimum size such as in quantum computing and nanotechnology.

The purpose of this paper is to introduce new implementations for parallel processing applications using bijective systolic networks and the corresponding carbon-based field emission controlled switching. The developed implementations are performed in the reversible domain to perform the required bijective parallel computing, where the implementations for parallel computations that utilize the presented field-emission controlled switching and their corresponding m-ary (many-valued) extensions for the use in nano systolic networks are introduced. The first part of the paper presents important fundamentals with regards to systolic computing and carbon-based field emission that will be utilized in the implementations within the second part of the paper.

The introduced systolic systems utilize recent findings in field emission and nano applications to implement the functionality of the basic bijective systolic network. This includes many-valued systolic computing via field emission techniques using carbon-based nanotubes and nanotips. The realization of bijective logic circuits in current and emerging technologies can be very important for various reasons. The reduction of power consumption is a major requirement for the circuit design in future technologies, and thus, the new nano systolic circuits can play an important role in the design of circuits that consume minimal power for future applications such as in low-power signal processing. In addition, the implemented bijective systems can be utilized to implement massive parallel processing and thus obtaining very high processing performance, where the implementation will also utilize the significant size reduction within the nano domain. The extensions of implementations to field emission-based many-valued systolic networks using the introduced bijective nano systolic architectures are also presented.

Novel bijective systolic architectures using nano-based field emission implementations are introduced in this paper, and the implementation using the general scheme of many-valued computing is presented. The carbon-based field emission implementation of nano systolic networks is also introduced. This is accomplished using the introduced field emission carbon-based devices, where field emission from carbon nanotubes and nano-apex carbon fibers is utilized. The implementations of the many-valued bijective systolic networks utilizing the introduced nano-based architectures are also presented.

The introduced bijective systolic implementations form new important directions in the systolic realizations using the newly emerging nano-based technologies. The 2-to-1 multiplexer is a basic building block in “switch logic,” where in switch logic, a logic circuit is realized as a combination of switches rather than a combination of logic gates as in the gate logic, which proves to be less costly in synthesizing multiplexer-based wide variety of modern circuits and systems since nano implementations exist in very compact space where carbon-based devices switch reliably using much less power than silicon-based devices. The introduced implementations for nano systolic computation are new and interesting for the design in future nanotechnologies that require optimal design specifications of minimum power consumption and minimum size layout such as in low-power control of autonomous robots and in the adiabatic low-power very-large-scale-integration circuit design for signal processing applications.

The purpose of this paper is to introduce new non‐classical implementations of neural networks (NNs). The developed implementations are performed in the quantum, nano, and optical domains to perform the required neural computing. The various implementations of the new NNs utilizing the introduced architectures are presented, and their extensions for the utilization in the non‐classical neural‐systolic networks are also introduced.

The introduced neural circuits utilize recent findings in the quantum, nano, and optical fields to implement the functionality of the basic NN. This includes the techniques of many‐valued quantum computing (MVQC), carbon nanotubes (CNT), and linear optics. The extensions of implementations to non‐classical neural‐systolic networks using the introduced neural‐systolic architectures are also presented.

Novel NN implementations are introduced in this paper. NN implementation using the general scheme of MVQC is presented. The proposed method uses the many‐valued quantum orthonormal computational basis states to implement such computations. Physical implementation of quantum computing (QC) is performed by controlling the potential to yield specific wavefunction as a result of solving the Schrödinger equation that governs the dynamics in the quantum domain. The CNT‐based implementation of logic NNs is also introduced. New implementations of logic NNs are also introduced that utilize new linear optical circuits which use coherent light beams to perform the functionality of the basic logic multiplexer by utilizing the properties of frequency, polarization, and incident angle. The implementations of non‐classical neural‐systolic networks using the introduced quantum, nano, and optical neural architectures are also presented.

The introduced NN implementations form new important directions in the NN realizations using the newly emerging technologies. Since the new quantum and optical implementations have the advantages of very high‐speed and low‐power consumption, and the nano implementation exists in very compact space where CNT‐based field effect transistor switches reliably using much less power than a silicon‐based device, the introduced implementations for non‐classical neural computation are new and interesting for the design in future technologies that require the optimal design specifications of super‐high speed, minimum power consumption, and minimum size, such as in low‐power control of autonomous robots, adiabatic low‐power very‐large‐scale integration circuit design for signal processing applications, QC, and nanotechnology.

New approaches for non‐classical neural‐based computing are introduced. The developed approaches utilize new concepts in three‐dimensionality, invertibility and reversibility to perform the required neural computing. The various implementations of the new neural circuits using the introduced paradigms and architectures are presented, several applications are shown, and the extension for the utilization in neural‐systolic computing is also introduced.

The new neural paradigms utilize new findings in computational intelligence and advanced logic synthesis to perform the functionality of the basic neural network (NN). This includes the techniques of three‐dimensionality, invertibility and reversibility. The extension of implementation to neural‐systolic computing using the introduced reversible neural‐systolic architecture is also presented.

Novel NN paradigms are introduced in this paper. New 3D paradigm of NL circuits called three‐dimensional inverted neural logic (3DINL) circuits is introduced. The new 3D architecture inverts the inputs and weights in the standard neural architecture: inputs become bases on internal interconnects, and weights become leaves of the network. New reversible neural network (RevNN) architecture is also introduced, and a RevNN paradigm using supervised learning is presented. The applications of RevNN to multiple‐output feedforward discrete plant control and to reversible neural‐systolic computing are also shown. Reversible neural paradigm that includes reversible neural architecture utilizing the extended mapping technique with an application to the reversible solution of the maze problem using the reversible counterpropagation NN is introduced, and new neural paradigm of reversibility in both architecture and training using reversibility in independent component analysis is also presented.

Since the new 3D NNs can be useful as a possible optimal design choice for compacting a learning (trainable) circuit in 3D space, and because reversibility is essential in the minimal‐power computing as the reduction of power consumption is a main requirement for the circuit synthesis of several emerging technologies, the introduced methods for non‐classical neural computation are new and interesting for the design of several future technologies that require optimal design specifications such as three‐dimensionality, regularity, super‐high speed, minimum power consumption and minimum size such as in low‐power control, adiabatic signal processing, quantum computing, and nanotechnology.

A novel many‐valued decomposition within the framework of lossless reconstructability analysis (RA) is presented. In previous work, modified reconstructability analysis (MRA) was applied to Boolean functions, where it was shown that most Boolean functions not decomposable using conventional reconstructability analysis (CRA) are decomposable using MRA. Also, it was previously shown that whenever decomposition exists in both MRA and CRA, MRA yields simpler or equal complexity decompositions. In this paper, MRA is extended to many‐valued logic functions, and logic structures that correspond to such decomposition are developed. It is shown that many‐valued MRA can decompose many‐valued functions when CRA fails to do so. Since real‐life data are often many‐valued, this new decomposition can be useful for machine learning and data mining. Many‐valued MRA can also be applied for the decomposition of relations.

Modified reconstructability analysis (MRA), a novel decomposition technique within the framework of set‐theoretic (crisp possibilistic) reconstructability analysis, is applied to three‐variable NPN‐classified Boolean functions. MRA is superior to conventional reconstructability analysis, i.e. it decomposes more NPN functions. MRA is compared to Ashenhurst‐Curtis (AC) decomposition using two different complexity measures: log‐functionality, a measure suitable for machine learning, and the count of the total number of two‐input gates, a measure suitable for circuit design. MRA is superior to AC using the first of these measures, and is comparable to, but different from AC, using the second.

Modified reconstructability analysis (MRA) can be realized reversibly by utilizing Boolean reversible (3,3) logic gates that are universal in two arguments. The quantum computation of the reversible MRA circuits is also introduced. The reversible MRA transformations are given a quantum form by using the normal matrix representation of such gates. The MRA‐based quantum decomposition may play an important role in the synthesis of logic structures using future technologies that consume less power and occupy less space.