Search results

In line with the recent development of flip-chip reliability and underfill process, this paper aims to comprehensively investigate the effect of different hourglass shape solder joint on underfill encapsulation process by mean of experimental and numerical method.

Lattice Boltzmann method (LBM) numerical was used for the three-dimensional simulation of underfill process. The effects of ball grid arrays (BGA) encapsulation process in terms of filling time of the fluid were investigated. Experiments were then carried out to validate the simulation results.

Hourglass shape solder joint has shown the shortest filling time for underfill process compared to truncated sphere. The underfill flow obtained from both simulation and experimental results are found to be in good agreement for the BGA model studied. The findings have also shown that the filling time of Hourglass 2 with parabolic shape gives faster filling time compared to the Hourglass 1 with hemisphere angle due to bigger cross-sectional area of void between the solder joints.

This paper provides reliable insights to the effect of hourglass shape BGA on the encapsulation process that will benefit future development of BGA packages.

LBM numerical method was implemented in this research to study the flow behaviour of an encapsulation process in term of filling time of hourglass shape BGA. To date, no research has been found to simulate the hourglass shape BGA using LBM.

This paper aims to determine the optimum set of temperatures through correlation study to attain the most effective capillary flow of underfill in a multi-stack ball grid array (BGA) chip device.

Finite volume method is implemented in the simulation. A three-layer multi-stack BGA is modeled to simulate the underfill flow. The simulated models were well validated with the previous experimental work on underfill process.

The completion filling time shows high regression R-squared value of up to 0.9918, which indicates a substantial acceleration on the underfill process because of incorporation of thermal delta. An introduction of 11 °C thermal delta to the multi-stacks BGA managed to reduce the filling time by up to 16.4%.

Temperature-induced capillary flow is a relatively new type of driven underfill designed specifically for package on package BGA components. Its simple implementation can further improve the productivity of existing underfill process in the industry that is desirable in reducing the process lead time.

The effect of temperature-induced capillary flow in underfill encapsulation on multi-stacks BGA by means of statistical correlation study is a relatively new topic, which has never been reported in any other research according to the authors’ knowledge.

This paper aims to study the filling progression of underfill flow and void formation during the flip-chip encapsulation process.

A new parameter of filling progression that relates volume fraction filled to filling displacement was formulated analytically. Another indicative parameter of filling efficiency was also introduced to quantify the voiding fraction in filling progression. Additionally, the underfill process on different flip-chips based on the past experiments was numerically simulated.

All findings were well-validated with reference to the past experimental results, in terms of quantitative filling progression and qualitative flow profiles. The volume fraction filled increases monotonically with the filling displacement and thus the filling time. As the underfill fluid advances, the size of the void decreases while the filling efficiency increases. Furthermore, the void formed during the underfilling flow stage was caused by the accelerated contact line jump at the bump entrance.

The filling progression enabled manufacturers to forecast the underfill flow front, as it advances through the flip-chip. Moreover, filling progression and filling efficiency could provide quantitative insights for the determination of void formations at any filling stages. The voiding formation mechanism enables the prompt formulation of countermeasures.

Both the filling progression and filling efficiency are new indicative parameters in quantifying the performance of the filling process while considering the reliability defects such as incomplete filling and voiding.

This paper aims to study the relationship between the ball grid array (BGA) flip-chip underfilling process parameter and its void formation region.

A set of top-down scanning acoustic microscope images of BGA underfill is collected and void labelled. The labelled images are trained with a convolutional neural network model, and the performance is evaluated. The model is tested with new images, and the void area with its region is analysed with its dispensing parameter.

All findings were well-validated with reference to the past experimental results regarding dispensing parameters and their quantitative regional formation. As the BGA is non-uniform, 85% of the test samples have void(s) formed in the emptier region. Furthermore, the highest rating factor, valve dispensing pressure with a Gini index of 0.219 and U-type dispensing pattern set of parameters generally form a lower void percentage within the underfilling, although its consistency is difficult to maintain.

This study enabled manufacturers to forecast the void regional formation from its filling parameters and array pattern. The filling pressure, dispensing pattern and BGA relations could provide qualitative insights to understand the void formation region in a flip-chip, enabling the prompt to formulate countermeasures to optimise voiding in a specific area in the underfill.

The void regional formation in a flip-chip underfilling process can be explained quantitatively with indicative parameters such as valve pressure, dispensing pattern and BGA arrangement.

This paper aims to introduce a new indicative parameter of filling efficiency to quantify the performance and productivity of the flip-chip underfill encapsulation process. Additionally, the variation effect of the bump pitch of flip-chip on the filling efficiency was demonstrated to provide insight for flip-chip design optimization.

The filling efficiency was formulated analytically based on the conceptual spatial and temporal perspectives. Subsequently, the effect of bump pitch on filling efficiency was studied based on the past actual-scaled and current scaled-up underfill experiments. The latter scaled-up experiment was validated with both the finite volume method-based numerical simulation and analytical filling time model. Moreover, the scaling validity of scaled-up experiment was justified based on the similarity analysis of dimensionless number.

Through the scaling analysis, the current scaled-up experimental system is justified to be valid since the adopted scaling factor 40 is less than the theoretical scaling limit of 270. Furthermore, the current experiment was qualitatively well validated with the numerical simulation and analytical filling time model. It is found that the filling efficiency increases with the bump pitch, such that doubling the bump pitch would triple the efficiency.

The new performance indicative index of filling efficiency enables the package designers to justify the variation effect of underfill parameter on the overall underfill process. Moreover, the upper limit of scaling factor for scaled-up package was derived to serve as the guideline for future scaled-up underfill experiments.

The performance of underfill process as highlighted in this paper was never being quantified before in the past literatures. Similarly, the scaling limit that is associated to the scaled-up underfill experiment was never being reported elsewhere too.

This paper aims to present experimental and finite volume method (FVM)-based simulation studies on the scaling effect on the capillary contact angle and entrant pressure for a three-dimensional encapsulation process of ball-grid array (BGA).

With the development of various sizes of BGA packages, the scaling effect of BGA model on capillary underfill (CUF) process is investigated together with the influences of different industrial standard solder bump arrangements and dispensing methods used as case study.

The experimental results agree well to the simulation findings with minimal deviation in filling time and similar flow front profiles for all setups. The results revealed that the capillary contact angle of flow front decreases in scale-up model with larger gap height observed and lengthens the encapsulation process. Statistical correlation studies are conducted and accurate regression equations are obtained to relate the gap height to the completion filling time and contact angle. CUF threshold capillary pressures were computed based on Leverett-J function and found to be increasing with the scale size of the package.

These statistical data provide accurate insights into the impact of BGA’s scale sizes to the CUF process that will be benefiting the future design of BGA package. This study provided electronic designers with profound understanding on the scaling effect in CUF process of BGA, which may be extended to the future development of miniature-sized BGA and multi-stack device.

This study relates the flow behaviour of encapsulant to its capillary contact angle and Leverett-J pressure threshold, in the CUF process of different BGA and dispensing conditions. To date, no research has been found to predict the threshold pressure on the gap between the chip and substrate.

This study aims to investigate crack propagation in a moisture-preconditioned soft-termination multi-layer ceramic capacitor (MLCC) during thermal reflow process.

Experimental and extended finite element method (X-FEM) numerical analyses were used to analyse the soft-termination MLCC during thermal reflow. A cross-sectional field emission scanning electron microscope image of an actual MLCC’s crack was used to validate the accuracy of the simulation results generated in the study.

At 270°C, micro-voids between the copper-electrode and copper-epoxy layers absorbed 284.2 mm/mg³ of moisture, which generated 6.29 MPa of vapour pressure and caused a crack to propagate. Moisture that rapidly vaporises during reflow can cause stresses that exceed the adhesive/substrate interface’s adhesion strength of 6 MPa. Higher vapour pressure reduces crack development resistance. Thus, the maximum crack propagation between the copper-electrode and copper-epoxy layers at high reflow temperature was 0.077 mm. The numerical model was well-validated, as the maximum crack propagation discrepancy was 2.6%.

This research holds significant implications for the industry by providing valuable insights into the moisture-induced crack propagation mechanisms in soft-termination MLCCs during the reflow process. The findings can be used to optimise the design, manufacturing and assembly processes, ultimately leading to enhanced product quality, improved performance and increased reliability in various electronic applications. Moreover, while the study focused on a specific type of soft-termination MLCC in the reflow process, the methodologies and principles used in this research can be extended to other types of MLCC packages. The fundamental understanding gained from this study can be extrapolated to similar structures, enabling manufacturers to implement effective strategies for crack reduction across a wider range of MLCC applications.

The moisture-induced crack propagation in the soft-termination MLCC during thermal reflow process has not been reported to date. X-FEM numerical analysis on crack propagation have never been researched on the soft-termination MLCC.

This paper aims to study the interfacial delamination found in the boundary of the copper/copper-epoxy layers of a multi-layer ceramic capacitor.

The thermal reflow process of the capacitor assembly and the crack propagation from the initial micro voids presented in the boundary, and later manifested into delamination, were numerically simulated. Besides, the cross section of the capacitor assembly was inspected for delamination cracks and voids using a scanning electronic microscope.

Interfacial delamination in the boundary of copper/copper-epoxy layers was caused by the thermal mismatch and growth of micro voids during the thermal reflow process. The maximum deformation on the capacitor during reflow was 2.370 µm. It was found that a larger void would induce higher vicinity stress, mode I stress intensity factor, and crack elongation rate. Moreover, the crack extension increased with the exerted deformation until 0.3 µm, before saturating at the peak crack extension of around 0.078 µm.

The root cause of interfacial delamination issues in capacitors due to thermal reflow has been identified, and viable solutions proposed. These can eliminate the additional manufacturing cost and lead time incurred in identifying and tackling the issues; as well as benefit end-users, by promoting the electronic device reliability and performance.

To the best of the authors’ knowledge, the mechanism of delamination occurrence in a capacitor during has not been reported to date. The parametric variation analysis of the void size and deformation on the crack growth has never been conducted.

This study aims to investigate the design configuration for an optimum solder height of reinforced SAC305 solder joint in an ultra-fine capacitor assembly.

A multiphase finite volume model is developed for reflow soldering simulations to determine the fillet height of reinforced SAC305 solder joint in an ultra-fine capacitor assembly. Different solders, namely SAC305-x, SAC305-xNiO and SAC305-xTi, with varying percentage weight compositions of nanoparticles (x = 0 Wt.%, 0.01 Wt.%, 0.05 Wt.%, 0.10 Wt.%, 0.15 Wt.%) are investigated. A reflow soldering experiment is also conducted, and the cross-sections of the reflowed packages are examined using a High-Resolution Transmission Electron Microscope (HRTEM). The optimum design configurations (nanoparticle composition and material) for the solder fillet height are investigated using the Taguchi orthogonal array method.

Good correlations were recorded between the HRTEM micrographs and the numerical predictions of the nanoparticles' distribution in the molten solder. The numerical prediction of the fillet height also agrees with the experiment, with a maximum disparity of 5.43%. It was found that Ti nanoparticles, having the smallest density compared to NiO and, exhibit the highest buoyancy effect in the molten solder. The Taguchi analysis revealed that the nanoparticles' material factor is more significant than the Wt.% factor for an optimum fillet height. An optimum design configuration for fillet height was established as SAC 305–0.15 Wt.% Ti, corresponding to a 41.13% improvement of the plain SAC 305 solder.

The fillet height of solder joints greatly influences the solder joint reliability of miniaturized electronic packages. Solder joint reliability of ultra-fine capacitors can be improved using this study's findings on the optimum design configuration for the capacitor's solder fillet. The study’s findings can be practically implemented in industries such as electronics manufacturing, where enhanced solder joint reliability is critical.

Investigation of the optimum design configuration for reinforced SAC305 solder fillet is almost nonexistent in the literature. This study explored the optimization of fillet height of reinforced SAC305 solder joints in miniaturized capacitor assembly.

This study aims to investigate the possible defects and their root causes in a soft-termination multilayered ceramic capacitor (MLCC) when subjected to a thermal reflow process.

Specimens of the capacitor assembly were subjected to JEDEC level 1 preconditioning (85 °C/85%RH/168 h) with 5× reflow at 270°C peak temperature. Then, they were inspected using a 2 µm scanning electron microscope to investigate the evidence of defects. The reliability test was also numerically simulated and analyzed using the extended finite element method implemented in ABAQUS.

Excellent agreements were observed between the SEM inspections and the simulation results. The findings showed evidence of discontinuities along the Cu and the Cu-epoxy layers and interfacial delamination crack at the Cu/Cu-epoxy interface. The possible root causes are thermal mismatch between the Cu and Cu-epoxy layers, moisture contamination and weak Cu/Cu-epoxy interface. The maximum crack length observed in the experimentally reflowed capacitor was measured as 75 µm, a 2.59% difference compared to the numerical prediction of 77.2 µm.

This work's contribution is expected to reduce the additional manufacturing cost and lead time in investigating reliability issues in MLCCs.

Despite the significant number of works on the reliability assessment of surface mount capacitors, work on crack growth in soft-termination MLCC is limited. Also, the combined experimental and numerical investigation of reflow-induced reliability issues in soft-termination MLCC is limited. These cited gaps are the novelties of this study.