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Publication date: 3 January 2017

Abderrazzak El Boukili

The purpose of this paper is to develop and apply accurate and original models to understand and analyze the effects of the fabrication temperatures on thermal-induced stress and…

115

Abstract

Purpose

The purpose of this paper is to develop and apply accurate and original models to understand and analyze the effects of the fabrication temperatures on thermal-induced stress and speed performance of nano positively doped metal oxide semiconductor (pMOS) transistors.

Design/methodology/approach

The speed performances of nano pMOS transistors depend strongly on the mobility of holes, which itself depends on the thermal-induced extrinsic stress σ. The author uses a finite volume method to solve the proposed system of partial differential equations needed to calculate the thermal-induced stress σ accurately.

Findings

The thermal extrinsic stress σ depends strongly on the thermal intrinsic stress σ0, thermal intrinsic strain ε0, elastic constants C11 and C12 and the fabrication temperatures. In literature, the effects of fabrication temperatures on C11 and C12 needed to calculate thermal-induced stress σ0 have been ignored. The new finding is that if the effects of fabrication temperatures on C11 and C12 are ignored, then, the values of stress σ0 and σ will be overestimated and, then, not accurate. Another important finding is that the speed performance of nano pMOS transistors will increase if the fabrication temperature of silicon-germanium films used as stressors is increased.

Practical implications

To predict correctly the thermal-induced stress and speed performance of nano pMOS transistors, the effects of fabrication temperatures on the elastic constants required to calculate the thermal-induced intrinsic stress σ0 should be taken into account.

Originality/value

There are three levels of originalities. The author considers the effects of the fabrication temperatures on extrinsic stress σ, intrinsic stress σ0 and elastic constants C11 and C12.

Details

COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, vol. 36 no. 1
Type: Research Article
ISSN: 0332-1649

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Article
Publication date: 1 December 1999

Abderrazzak El Boukili

We present a semi‐quantum model including tunneling effects across an abrupt heterojunction. The discontinuity of the effective masses and the energy bands are considered. The…

439

Abstract

We present a semi‐quantum model including tunneling effects across an abrupt heterojunction. The discontinuity of the effective masses and the energy bands are considered. The quantum transmission conditions for the quasi‐Fermi levels are obtained using WKB approximation. We use mixed finite element approach and a two dimensional mesh which is double‐valued for quasi‐Fermi levels at a heterojunction. A GaAs/GaAIAs heterojunction diode is then simulated using both drift‐diffusion and semi‐quantum model by varying doping density at low temperature.

Details

COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, vol. 18 no. 4
Type: Research Article
ISSN: 0332-1649

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Article
Publication date: 28 October 2014

Abderrazzak El Boukili

The purpose of this paper is to provide a new three dimension physically based model to calculate the initial stress in silicon germanium (SiGe) film due to thermal mismatch after…

64

Abstract

Purpose

The purpose of this paper is to provide a new three dimension physically based model to calculate the initial stress in silicon germanium (SiGe) film due to thermal mismatch after deposition. We should note that there are many other sources of initial stress in SiGe films or in the substrate. Here, the author is focussing only on how to model the initial stress arising from thermal mismatch in SiGe film. The author uses this initial stress to calculate numerically the resulting extrinsic stress distribution in a nanoscale PMOS transistor. This extrinsic stress is used by industrials and manufacturers as Intel or IBM to boost the performances of the nanoscale PMOS and NMOS transistors. It is now admitted that compressive stress enhances the mobility of holes and tensile stress enhances the mobility of electrons in the channel.

Design/methodology/approach

During thermal processing, thin film materials like polysilicon, silicon nitride, silicon dioxide, or SiGe expand or contract at different rates compared to the silicon substrate according to their thermal expansion coefficients. The author defines the thermal expansion coefficient as the rate of change of strain with respect to temperature.

Findings

Several numerical experiments have been used for different temperatures ranging from 30 to 1,000°C. These experiments did show that the temperature affects strongly the extrinsic stress in the channel of a 45 nm PMOS transistor. On the other hand, the author has compared the extrinsic stress due to lattice mismatch with the extrinsic stress due to thermal mismatch. The author found that these two types of stress have the same order (see the numerical results on Figures 4 and 12). And, these are great findings for semiconductor industry.

Practical implications

Front-end process induced extrinsic stress is used by manufacturers of nanoscale transistors as the new scaling vector for the 90 nm node technology and below. The extrinsic stress has the advantage of improving the performances of PMOSFETs and NMOSFETs transistors by enhancing mobility. This mobility enhancement fundamentally results from alteration of electronic band structure of silicon due to extrinsic stress. Then, the results are of great importance to manufacturers and industrials. The evidence is that these results show that the extrinsic stress in the channel depends also on the thermal mismatch between materials and not only on the material mismatch.

Originality/value

The model the author is proposing to calculate the initial stress due to thermal mismatch is novel and original. The author validated the values of the initial stress with those obtained by experiments in Al-Bayati et al. (2005). Using the uniaxial stress generation technique of Intel (see Figure 2). Al-Bayati et al. (2005) found experimentally that for 17 percent germanium concentration, a compressive initial stress of 1.4 GPa is generated inside the SiGe layer.

Details

COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering, vol. 33 no. 6
Type: Research Article
ISSN: 0332-1649

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