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Article
Publication date: 1 August 1996

R. Aschenbrenner, E. Zakel, G. Azdasht**, A. Kloeser and H. Reichl

During the last few years an increasing number of flip‐chip (FC) interconnection technologies have emerged. While flip‐chip assembly offers many advantages compared with…

660

Abstract

During the last few years an increasing number of flip‐chip (FC) interconnection technologies have emerged. While flip‐chip assembly offers many advantages compared with conventional packaging techniques, several aspects prevent this technology from entering the high volume market. Among these are the availability of bumped chips and the costs of the substrates, i.e., ceramic substrates with closely matching coefficient of thermal expansion (CTE) to the chip, in order to maintain high reliability. Only recently, with the possibility of filling the gap between chip and organic substrate with an encapsulant, was the reliability of flip‐chips mounted on organic substrates significantly enhanced. This paper presents two approaches to a fluxless process, one based on soldering techniques using Au‐Sn metallurgy and the other on adhesive joining techniques. Soldering is performed with a thermode and with a laser based system. For both of these FC‐joining processes, alternative bump mettallurgies based on electroplated gold, electroplated gold‐tin, mechanical gold and electroless nickel gold bumps are applied.

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Soldering & Surface Mount Technology, vol. 8 no. 2
Type: Research Article
ISSN: 0954-0911

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Article
Publication date: 3 February 2012

Robert Kay and Marc Desmulliez

The purpose of this paper is to present a detailed overview of the current stencil printing process for microelectronic packaging.

1318

Abstract

Purpose

The purpose of this paper is to present a detailed overview of the current stencil printing process for microelectronic packaging.

Design/methodology/approach

This paper gives a thorough review of stencil printing for electronic packaging including the current state of the art.

Findings

This article explains the different stencil technologies and printing materials. It then examines the various factors that determine the outcome of a successful printing process, including printing parameters, materials, apparatus and squeegees. Relevant technical innovations in the art of stencil printing for microelectronics packaging are examined as each part of the printing process is explained.

Originality/value

Stencil printing is currently the cheapest and highest throughput technique to create the mechanical and electrically conductive connections between substrates, bare die, packaged chips and discrete components. As a result, this process is used extensively in the electronic packaging industry and therefore such a review paper should be of interest to a large selection of the electronics interconnect and assembly community.

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Soldering & Surface Mount Technology, vol. 24 no. 1
Type: Research Article
ISSN: 0954-0911

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Article
Publication date: 1 April 2000

David A. Hutt, Daniel G. Rhodes, Paul P. Conway, Samjid H. Mannan, David C. Whalley and Andrew S. Holmes

As the demand for flip‐chip products increases, the need for low cost high volume manufacturing processes also increases. Currently solder paste printing is the wafer bumping…

389

Abstract

As the demand for flip‐chip products increases, the need for low cost high volume manufacturing processes also increases. Currently solder paste printing is the wafer bumping method of choice for device pitches down to 150‐200μm. However, limitations in print quality and stencil manufacture mean that this technology is not likely to move significantly below this pitch and new methods will be required to meet the demands predicted by the technology roadmaps. This paper describes experiments conducted on carriers made from silicon for bumping of die using solder paste. An anisotropic etching process was used to generate pockets in the silicon surface into which solder paste was printed. Die were then placed against the carrier and reflowed to transfer the solder directly to the bondpads. An assessment was carried out of the potential application and limitations of this technique for device pitches at 225 and 127μm.

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Soldering & Surface Mount Technology, vol. 12 no. 1
Type: Research Article
ISSN: 0954-0911

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Article
Publication date: 1 April 2014

Robert W. Kay, Gerard Cummins, Thomas Krebs, Richard Lathrop, Eitan Abraham and Marc Desmulliez

Wafer-level stencil printing of a type-6 Pb-free SAC solder paste was statistically evaluated at 200 and 150 μm pitch using three different stencil manufacturing technologies…

184

Abstract

Purpose

Wafer-level stencil printing of a type-6 Pb-free SAC solder paste was statistically evaluated at 200 and 150 μm pitch using three different stencil manufacturing technologies: laser cutting, DC electroforming and micro-engineered electroforming. This investigation looks at stencil differences in printability, pitch resolution, maximum achievable bump height, print co-planarity, paste release efficiency, and cleaning frequency. The paper aims to discuss these issues.

Design/methodology/approach

In this paper, the authors present a statistical evaluation of the impact of stencil technology on type-6 tin-silver-copper paste printing. The authors concentrate on performances at 200 and 150 μm pitch of full array patterns. Key evaluated criteria include achievable reflowed bump heights, deposit co-planarity, paste release efficiency, and frequency of stencil cleaning. Box plots were used to graphically view print performance over a range of aperture sizes for the three stencil types.

Findings

Fabrication technologies significantly affect print performance where the micro-engineered electroformed stencil produced the highest bump deposits and the lowest bump height deviation. Second in performance was the conventional electroformed, followed by the laser-cut stencil. Comparisons between the first and fifth consecutive print demonstrated no need for stencil cleaning in the case for the micro-engineered stencil for all but the smallest spacings between apertures. High paste transfer efficiencies, i.e. above 85 per cent, were achieved with the micro-engineered stencil using low aperture area ratios of 0.5.

Originality/value

Stencil technology influences the maximum reflowed solder bump heights achievable, and bump co-planarity. To date, no statistical analysis comparing the impact of stencil technology for wafer-level bumping has been carried out for pitches of 200 μm and below. This paper gives new insight into how stencil technology impacts the print performance for fine pitch stencil printing. The volume of data collected for this investigation enabled detailed insight into the limitations of the printing process and as a result for suitable design guidelines to be developed. The finding also shows that the accepted industry guidelines on stencil design developed by the surface mount industry can be broken if the correct stencil technology is selected, thereby increasing the potential application areas of stencil printing.

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Soldering & Surface Mount Technology, vol. 26 no. 2
Type: Research Article
ISSN: 0954-0911

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Article
Publication date: 1 March 2003

Changqing Liu and David A. Hutt

The solder interconnection of components to printed circuit boards normally utilises a flux to enable the efficient removal of oxide layers from the metals to be joined. While…

637

Abstract

The solder interconnection of components to printed circuit boards normally utilises a flux to enable the efficient removal of oxide layers from the metals to be joined. While this produces a strong metallurgical bond, the flux residue left behind after the soldering process can be detrimental to the long‐term performance of the product. Therefore, after assembly, a cleaning process is often employed to remove the residue, however, this incurs extra financial and environmental costs. In this work, organic coatings have been used to preserve copper surfaces in an oxide free state, enabling fluxless soldering to take place. These coatings, if stored appropriately, were found to be effective in preventing the oxidation of copper for several weeks, however, they are readily displaced by the soldering process allowing the active copper surface to be wetted. Wetting balance testing and surface analysis have been used to assess the preservation of copper coupons following storage in air.

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Circuit World, vol. 29 no. 1
Type: Research Article
ISSN: 0305-6120

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Article
Publication date: 1 March 1993

E. Zakel, J. Kloeser, H. Distler and H. Reichl

Due to increasing density and high demands on electrical and thermal performance, modern packages require alternative chip interconnection and substrate technologies. Flip‐chip…

48

Abstract

Due to increasing density and high demands on electrical and thermal performance, modern packages require alternative chip interconnection and substrate technologies. Flip‐chip (FC) bonding is a suitable method for high interconnection densities. Compared with wire bonding and TAB, FC provides the highest contact density. This is due to the possibility of using the whole chip surface for bondpads (area bumps). In this paper, an adapted FC technology on green tape ceramic substrates was investigated. In order to reduce the substrate costs, FC bonding was performed directly on the thick film metallisation without the application of thin film technology for the upper substrate layers. Two solder bump metallurgies: PbSn95/5 and Au/Sn solder bumps were applied for fluxless FC bonding on adapted substrate metallisations. Fluxless soldering is performed by single chip bonding and requires substrates with narrow planarity tolerances. An alternative method using a wet eutectic Au/Sn solder paste on the substrate and Au bumps permits the application of substrates with standard planarity tolerances used in thick film applications. A common reflow of all chips of a multichip module is possible. First reliability results of metallurgical analysis and of the mechanical and electrical behaviour of the FC contacts after thermal cycling are presented.

Details

Microelectronics International, vol. 10 no. 3
Type: Research Article
ISSN: 1356-5362

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Article
Publication date: 1 September 2000

J. Kloeser and W. Scheel

The evolution of IC manufacturing technology has led to a decrease in feature size on the silicon die from around 2μm nowadays down to 0.18μm, and in the near future down to…

481

Abstract

The evolution of IC manufacturing technology has led to a decrease in feature size on the silicon die from around 2μm nowadays down to 0.18μm, and in the near future down to 0.13μm. This implies a simultaneous decrease in the distance of the individual contact pads (pitch), decreasing from a moderate 0.5mm to nowadays 0.1mm or even 0.07mm for leading edge ICs. The near future will not allow this trend to continue. Instead of peripheral contacts, several rows of contacts or even use of the entire die area to accommodate the contacts will allow the numbers of IOs to increase to the required value. Following the roadmap of electronic devices the PCB has its design continuously changed. Accordingly we need today PCBs with high density interconnects, realized by sequential build‐up technology (SBU) including microvias. We see at the end of the next decade that the semiconductor technology will be introduced at the PCB level. At this time we are also able to transfer the chip design into the PCB directly. This dependence of the development from chip‐ and PCB‐technology is the subject of the paper.

Details

Circuit World, vol. 26 no. 3
Type: Research Article
ISSN: 0305-6120

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Article
Publication date: 1 August 2000

Zhaowei Zhong

Discusses three simple and low‐cost flip chip assembly processes. First, flip chip on board using non‐conductive adhesive is evaluated. This process can give reasonable…

256

Abstract

Discusses three simple and low‐cost flip chip assembly processes. First, flip chip on board using non‐conductive adhesive is evaluated. This process can give reasonable reliability and high assembly yield, when the parameters for epoxy placement and bonding are optimised. Second, the flip chip assembly process using reflowable no‐flow underfill is discussed. Because the underfill epoxy is already placed in the gap between the IC chip and the substrate before reflow, it is not easy to control the solder joints’ collapse and obtain the desired solder‐joint shapes and stand‐off distance during reflow. Finally, the stud bump bonding process is also discussed. It is not easy although possible to maintain the optimal dipping of the conductive adhesive, when the average height of the gold bumps is small. Some solutions for overcoming the above‐mentioned difficulties are presented in this paper.

Details

Microelectronics International, vol. 17 no. 2
Type: Research Article
ISSN: 1356-5362

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Article
Publication date: 27 June 2008

Christopher M. Greene and Krishnaswami Srihari

Environmental concerns over hazardous materials being placed in landfills have caused many countries to enact legislation to limit and/or eliminate the use of lead in electronic…

337

Abstract

Purpose

Environmental concerns over hazardous materials being placed in landfills have caused many countries to enact legislation to limit and/or eliminate the use of lead in electronic devices. As a result, the electronics manufacturing industry has undertaken efforts to comply with the legislation. Solder paste is typically used as the joining material between boards and components. The standard solder paste alloy has traditionally been a tin/lead eutectic. Lead‐free should, in theory, have the same functionality as the standard pastes to be utilized as a drop‐in replacement. Typically, solder paste is deposited on to a land pattern site by a stencil printer. In the manufacturing environment, speed and accuracy are desirable characteristics of the stencil printing operation. The purpose of this paper is to determine how fast a selection of lead‐free pastes can be successfully printed.

Design/methodology/approach

A representative sample of four lead‐free solder pastes containing different alloys was selected. A series of experiments at an increasing print speed was used to deposit these solder pastes on to printed circuit boards and the printed solder volumes were measured. The maximum print speed for each paste was observed and noted for future use.

Findings

Of the four alloys selected for experimentation, one emerged to have the most superior performance in terms of high‐speed printability. The speeds for each paste were observed and noted for future use.

Research limitations/implications

Experimentation was performed in an electronics service provider's environment using equipment and materials that were normally used in production.

Practical implications

The parameters obtained can be used on the manufacturing floor assembling lead‐free products.

Originality/value

The results offer a suggestion (in the form of the parameters that can be utilized) as to what parameters to use in the stencil printing of lead‐free solder paste at high speeds.

Details

Soldering & Surface Mount Technology, vol. 20 no. 3
Type: Research Article
ISSN: 0954-0911

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Article
Publication date: 1 December 1999

Zhaowei Zhong

Reports the research and development results on flip chip on FR‐4 and ceramics, using anisotropic conductive film (ACF), anisotropic conductive paste (ACP), or eutectic solder…

326

Abstract

Reports the research and development results on flip chip on FR‐4 and ceramics, using anisotropic conductive film (ACF), anisotropic conductive paste (ACP), or eutectic solder with underfill. Several types of ACF and ACP with different types of conductive particles and adhesives were investigated. Simple but high yield procedures for reworking flip chip on board using ACP and ACF were developed. Processes for flip chip on FR‐4 and ceramic boards using eutectic solder bumps with underfill were also evaluated. The flip chips were assembled on test vehicles for temperature cycling and high‐temperature high‐humidity tests. The reliability performance of the three processes (gold bumps with ACF, gold bumps with ACP, and eutectic solder bumps with underfill) is compared.

Details

Microelectronics International, vol. 16 no. 3
Type: Research Article
ISSN: 1356-5362

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