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Recent progress in silicon—on—insulator (SOI) technologies has made possible the fabrication of high quality ultra—thin film structures. Preliminary research has demonstrated the advantage of fully—depleted SOI MOSFET's in term of speed and improved resistance to hot carrier degradation. The specific dual‐gate configuration of SOI transistors is schematically presented in Fig. 1(a).

As the physical dimensions of the devices are reduced to the submicrometer regime, the hot‐carrier reliability has become an important issue in the scaling of the p‐MOSFET as well as the n‐MOSFET. In this paper, we present a unified approach for p‐MOSFET degradation due to the trapping of the hot electrons in the gate oxide layers. A physical analytical model, based on the pseudo two‐dimensional model, is derived for the first time to describe the linear and saturation drain current degradation. The model has been verified by comparing the calculation and the measurement from submicron p‐MOSFET's with different channel lengths and oxide thickness. There are no empirical parameters in the model. Two physical parameters: the capture cross section and the density of states of electron traps, which can be determined independently from the measured degradation characteristics, are valid for both the linear current and the saturation current degradation. The simple expression is very suitable for the predicting of the circuit reliability.