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This paper aims to propose a low-power complementary MOS (CMOS) current sensor for control circuit in an integrated DC-DC buck converter.

The integrated DC-DC converter, which is composed of feedback control circuit and power block, is designed with 0.35-µm CMOS process. Current sensor in the control circuit is integrated with sense-FET and voltage-follower circuits to reduce power consumption and improve its sensing accuracy. In the current-sensing circuit, the size ratio of the power metal oxide semiconductor field effect transistor (MOSFET) to the sensing transistor (K) is 1,000, and a current-mirror is used for a voltage follower. N-channel MOS acts as a switching device in the current-sensing circuit, where the sensing FET is in parallel with the power MOSFET. The amplifier and comparator are designed to obtain a high gain and a fast transient time.

Experiment shows that the current sensor is operated with accuracy of more than 85 per cent, and the transient time of the error amplifier is controlled within 100 µs. The sensing current is in the range of a few hundred µA at a frequency of 0.6-2 MHz and an input voltage of 3-5 V. The output voltage is obtained as expected with the ripple ratio within 5 per cent.

The proposed current sensor in DC-DC converter provides an accurately sensed inductor current with a significant reduction in power consumption in the range of 0.2 mW. High-accuracy regulation is obtained using the proposed current sensor. As the sensor utilizes simple switch-type voltage follower and sense-FET, it can be widely applied to other low-power applications such as high-frequency oscillator and over-current protection circuit.

The purpose of this paper is to describe the application of low‐glitch current cell in a digital to analog converter (DAC) to reduce the clock‐feedthrough effect and achieve a low power consumption.

A low‐glitch current switch cell is applied in a ten‐bit two‐stage DAC which is composed of a unary cell matrix for six most significant bits and a binary weighted array for four least significant bits (LSBs). The current cell is composed of four transistors to neutralize the clock‐feedthrough effect and it enables DAC to operate in good linearity and low power consumption. The prototype DAC is being implemented in a 0.35μm complementary metal‐oxide semiconductor process. The reduction in glitch energy and power consumption has been realized by preliminary experiment and simulation.

Compared to conventional current cell, more than 15 per cent reduction of glitch energy has been obtained in this work. The DAC is estimated that differential nonlinearity is within 0.1 LSB and the maximum power consumption is 68 mW at the sampling frequency of 100 MHz.

Comparison with other conventional work indicates that the current cell proposed in this paper shows much better performance in terms of switching spike and glitch, which may come from the extra dummy transistor in cell and reduce the clock‐feedthrough effect.

This paper aims to design the circuit for electromagnetic interface (EMI) reduction in liquid crystal display (LCD).

The cascode level shifter and segmented driver circuit are applied in LCD column driver integrated circuit (IC) for EMI reduction. Cascode current mirror is used in the proposed level shifter for DC voltage biasing and reduction of the driving current which passes through the level shifter. The on-off switching currents and transient times are measured and compared between the conventional and proposed level shifters. Additionally, a segmented data latch is obtained by the timing spread solution in data latch, and applied to split the large peak switching current into a number of smaller peak current. The timing spread-operation does not actually reduce the total power of the noise, instead, it spreads the noise power evenly over the frequency bandwidth. The optimal number of latch is dependent on the operating frequency and EMI allowance. The column driver IC and clock controller are integrated in 0.18 μm CMOS technology with 1-poly and 4-metal process.

The post-layout simulation shows that the proposed column driver circuit for LCD driver IC significantly reduces the peak switching current, and it results in the reduction of EMI noise level by more than 15 dB. It is obtained with 20 segmented operations in data latch at 40 MHz frequency.

The advantage of the cascode current source is that it can provide a well-controlled bias current with an accurate current transfer ratio. To reduce the EMI noise in LCD driver circuit, the cascode current source is properly located for the DC bias block in the level shifter. The application is rarely done by others, and a significant EMI noise reduction is found. The well-controlled current source provides a high performance switching in the level shifter.

The purpose of this paper is to present a fully integrated power converter. A stacked spiral inductor is applied in a voltage‐mode CMOS DC‐DC converter for the chip miniaturization and low‐power operation.

The three‐layer spiral inductor is simulated with an equivalent circuit and applied to the DC‐DC converter. The DC‐DC buck converter has been fabricated with a standard 0.35 μm CMOS process. The power converter is measured in both experiment and simulation in terms of frequency and electrical characteristics.

Experimental results show that the converter with the stacked spiral inductor operates properly with the inductance of 7.6 nH and mW power range. The measured inductance of the stacked spiral inductor is found to be almost half of the circuit designed value because of the parasitic resistances and capacitances in the spiral inductor.

This paper first introduces the application of the integrated stacked spiral inductor in DC‐DC buck converter for display driver circuit, which requires a low‐power operation. It also shows the fully integrated DC‐DC converter for chip miniaturization.

The purpose of this paper is to present the design and optimization of a comparator with two transistors.

The effect of back‐gate bias in MOSFET is analyzed and applied to a comparator circuit in a flash‐type A/D converter (ADC). The 4‐bit flash ADC is simply structured by change of comparator block based on CMOS latch with pMOSFET switch. The back‐gate bias on MOSFET changes the threshold voltage and provides for a CMOS inverter to shift the voltage transfer characteristics. In the new type comparator, the variation of turn‐on voltage is controlled within 0.1 V in 4‐bit ADC. The fabrication is done in a 0.35 μm single‐poly four‐metal process.

Layout simulation shows that INL is within 0.3 LSB and SNDR is 25.4 dB at input frequency of 20 KHz and sampling rate of 4 MS/s. The 0.26 × 0.43 mm 2 ADC dissipates 1.2 mW at supply voltage of 3.3 V.

A comparator which uses the effect of the back‐gate bias on MOSFET is applied to a flash ADC. The paper is of value in showing how the circuit of this comparator is quite simple compared with a conventional comparator based on a CMOS latch, which is adaptable for a low‐power analog circuit in future. The experimental output of the 4‐bit flash ADC shows a good agreement with a simulation. Power consumption 1.2 mW, INL 0.2 LSB, and SNDR 25 dB are obtained in the simulation study.

The purpose of this paper is to introduce a low power digital‐to‐analog converter (DAC) by using a sequential triggering technique in cascaded current source.

The block of current cell consists of current switch and source. A sequential switching on process is implemented with the current triggering technique in source. An experiment of 12‐b 150‐MS/s DAC has been integrated in a single‐poly four‐metal 0.35 μm CMOS process.

Compared with conventional cell array in 12‐b 150‐MS/s DAC, the proposed cell array shows that more than 30 percent of power consumption is reduced in full digital bit operation with allowable linearity error of 0.4 LSB.

This paper presents a new operation method of cell array in a current‐steering digital‐to‐analog converter (DAC) to reduce the power consumption significantly.

The paper aims to design of dual-mode boost converter with integrated low-voltage control circuit is introduced in this paper. The paper aims to discuss these issues.

The converter is operated either with LC filter or with charge pump circuit by the switch control. The control stage with error amplifier, comparator, and oscillator is designed with the supply voltage of 3.3 V and the operating frequency of 5.5 MHz. The compensator circuit exploits a pole compensation for a stable operation.

The simulation test in 0.35 μm CMOS process shows that the charge pump regulator and DC-DC boost converter are accurately controlled with the variation of number of stages and duty ratio. The output-voltage is obtained to be 6-15 V within the ripple ratio of 5 percent. Maximum power consumption is about 0.65 W.

This dual-mode is useful in the converter with a wide load-current variation. The advantage of the dual-mode converter is that it can be used in either high or low load current with a simple switch control. Furthermore, in charge pump regulator, there is no degradation of output voltage because of the feedback control circuit.