ARM and Synopsys collaborate to deliver optimised reference implementations for ARM processors

Citation

(2013), "ARM and Synopsys collaborate to deliver optimised reference implementations for ARM processors", Microelectronics International, Vol. 30 No. 3. https://doi.org/10.1108/mi.2013.21830caa.003

ARM and Synopsys collaborate to deliver optimised reference implementations for ARM processors

Article Type: Industry news From: Microelectronics International, Volume 30, Issue 3

ARM and Synopsys have announced the availability of optimised 28 nm Synopsys reference implementations for ARM Cortex-A15 MPCore and Cortex-A7 MPCore processor clusters as well as the CoreLink CCI-400 cache-coherent interconnect. The companies collaborated to deliver these optimised implementations in TSMC 28 high performance mobile (HPM) process technology using the Synopsys Galaxy Implementation Platform, ARM Artisan standard cells and memories, and ARM POP™ technology for core-hardening acceleration specifically optimised for Cortex-A15 and Cortex-A7 processor implementations. System on a chip (SoC) designers can use these reference implementations to create high performance Cortex-A15 and energy efficient Cortex-A7 processor clusters, and can combine them with the CCI-400 interconnect to create a big.LITTLE processing system that delivers increased product functionality with longer battery life.

Configured for ARM Cortex-A15 and Cortex-A7 processors as well as CCI-400 interconnect, the synopsys reference implementations provide tool scripts, a baseline floorplan, design constraints and documentation to serve as an optimised starting point for implementation. These scripts built on the widely-used synopsys tool reference methodologies (RMs) and optimised for high performance cores, leverage Galaxy Platform capabilities such as Design Compiler^® Graphical physical guidance for improved timing and post-route correlation. The scripts also leverage IC Compiler™ technologies, including final stage leakage recovery for reduced leakage power, data flow analysis for faster floorplan creation and transparent interface optimisation for faster top level closure. They are configured for TSMC 28HPM process technology with ARM Artisan standard cells, memories and ARM POP technology. Designers may further optimise the scripts for their own design goals, processor configurations, process technologies and libraries. Reference implementation technology plug-ins for the Synopsys Lynx Design System will enable a full, chip level production design flow. Synopsys also provides expert professional services to help designers deploy and customise the reference implementations to achieve their specific SoC design goals.

The Synopsys reference implementation for the Cortex-A7 processor cluster is for a quad-core MPCore configuration, optimised first for energy efficiency, then for maximum speed to provide energy efficient multi-processing. For high performance multi-processing within a tight power envelope, the reference implementation for the Cortex-A15 processor cluster targets a dual-core configuration, optimised first for performance, then for power. The CCI-400 interconnect implementation is optimised for the combination of these two processor clusters into a big.LITTLE processing system.

ARM and Synopsys have also collaborated on a reference verification platform for Synopsys Discovery Verification IP, which supports the ARM AMBA^® 4 ACE™ protocol and CCI-400 interconnect. With this reference verification platform, verification engineers can rapidly develop highly efficient verification environments for their cache-coherent designs.