Testing for the synergistic compatibility of process chemistries using surface insulation resistance measurements

Citation

(1999), "Testing for the synergistic compatibility of process chemistries using surface insulation resistance measurements", Circuit World, Vol. 25 No. 4. https://doi.org/10.1108/cw.1999.21725daf.001

Testing for the synergistic compatibility of process chemistries using surface insulation resistance measurements

Testing for the synergistic compatibility of process chemistries using surface insulation resistance measurements

Keywords: Printed circuit boards, Surface insulation resistance

During the manufacture of modern printed circuit boards a significant number of chemical processes and products are utilised, for example solder mask, fluxes (also in pastes and rework wire) and conformal coatings. Surface Insulation Resistance (SIR) has traditionally been used to prove that individual products in isolation provide an electrically insulating and electrochemically non-corrosive state. Here SIR measurement is used to test process permutations of a set of no-clean flux based products.

Currently in use in the PCB industry are a variety of standards based upon the Surface Insulation Resistance (SIR) test method[1,2]. The majority of these standards are utilised by product suppliers to qualify their flux or paste materials on standard test coupons using an interleaved comb pattern of tracks to model the tracks on a PCB. For example the IPC-B24 test coupon (Figure 1) carries four such comb patterns.

Figure 1 IPC B24 SIR test coupon

The work performed here is designed to represent actual process conditions as much as possible a surface mount SIR coupon similar to that used by the NPL was utilised. This test substrate has four comb patterns on it, but they are arranged to facilitate the mounting of SMT flat pack devices onto the board (Figure 2).

Figure 2 Concoat NPL based SMT coupon

This allows the coupons to be prepared for test using actual process settings, and with components mounted the effects of flux entrapment, and thermal mass are present. This is not the case for a flat test substrate.

Some chemicals, themselves giving good reliability individually, can cause low SIR levels by synergistic interactions[3]. To detect such occurrences SIR testing must be performed with all process chemistries present. Also in line with this philosophy both HASL and NiAu finishes were used in the testing, and the effects of a rework wire investigated.

The aim of the project is to provide a set of PCB production products with known compatibility under typical process conditions.

1. 1.

   Sample preparation ­ HASL finishSubmergence for five seconds at 255°C, standard proprietary flux used.

2. 2.

   Sample preparation ­ NiAu finishATOTECH Palladium activated NiAu. Bath temperature 88°C, 6g/litre Ni. Submergence for 25 minutes (4-6µ m Ni)

   The gold plating bath was controlled at 84°C, and submergence was for 12 minutes (0.06µ m Au).

3. 3.

   Sample preparation ­ permanent solder resistThe samples were pre-cleaned with a pumice scrub, and the mixed resist was applied through a 32.82 mesh screen. The resist is applied to the whole surface of the coupon. The samples were pre-dried at 85°C for 30 minutes before exposure to 450mJ/cm². The exposure pattern ensured only one QFP area on the test coupon was exposed, half the sample to remain free of mask after development (Figure 3).

   Figure 3 Exposed area of solder mask

   The un-exposed mask was removed using 1% Anhydrous K₂CO₃ at 35°C under 2.5 Bar of pressure.

   With a post-bake of one hour at 150°C the cured resist was 26µ m thick on the open board.

4. 4.

   Sample preparation ­ fluxThe flux was liberally applied to the test samples using a hand spray gun. The samples were then held vertically for 30 seconds on absorbent material to drain access flux.

   The alloy used in the wave was 63 percent Sn, 37 percent Pb at 250°C, and the samples were soldered in an air atmosphere (Figure 4).

   Figure 4 Wave temperature profile

5. 5.

   Sample preparation ­ pasteThe paste was applied using a DEK 260 screen printer with a ProFlo^TM solder cartridge system. The 0.006'' stainless steel stencil was designed to apply paste to the outer comb patterns to facilitate mounting of QFPs (Figure 5).

   Figure 5 Paste stencil design

   Although paste was deposited on both sites a QFP device was mounted only on the solder resist area of each SIR coupon, and was placed by hand. Reflow was at a peak of 222°C (Figure 6).

   Figure 6 Reflow temperature profile

6. 6.

   Sample preparation ­ mixed technologyTo model production of a mixed technology board the samples were spray fixed and passed over the wave comb-side up. Then the procedure for paste application was followed as above.

7. 7.

   Sample preparation ­ rework solder wireEach central comb pattern was soldered in four places with a small amount of solder wire. Solder was flowed onto tracks avoiding bridging. The tip temperature of the soldering iron was held at 350°C.

8. 8.

   SIR testingThe sample coupons were mounted into a 256-channel test rack, and connected to an Auto-SIR^TM automatic surface insulation resistance tester. The coupons were all labelled using a metal stamp so as not to introduce contamination onto the samples. The samples were handled with gloves at all times.

   The rack system holds 64 coupons, which require 256 (4 * 64) cables for connection. This is achieved with the Auto-SIR^TM system via a series of internally and externally grounded 34-way ribbon cables; in this case 16 were required each carrying 16 signals and 16 grounding wires.

   These precautions eliminate tribo-electric currents effecting the low current readings[4]. The samples were mounted into the test chamber to ensure even airflow over their surface, as recommended in ISO/PWI 9455-17[5].

   The chamber was set to ramp slowly to 40°C then a relative humidity 93 percent (according to IEC 68-2-20). Using this lower temperature condition (as opposed to the more traditional 85°C/85 percent RH condition) means, importantly, that any volatile components of no-clean fluxes (mainly organic acids) remain present throughout the test[6]. This is the recognised test condition for no-clean flux formulations, and these conditions were held for seven days. During this time a bias of 50V was applied to the coupons (relating to a voltage gradient of 125 V/mm on a track spacing of 0.4mm). The leakage current was measured and the Log Resistance value calculated and logged for every sample every ten minutes.

   At the end of the seven-day period the humidity was removed from the chamber before cooling so that at no point during the testing was condensation formed on the samples.

9. 9.

   SIR resultsThe results are correlated to the combination of process chemistries used to manufacture the samples. The IPC J-STD-001B Appendix D-5.3 states for SIR used in Material and Process Compatibility Testing ... "the minimum SIR value from each test vehicle ...shall be at least 1 × 10⁸ Ohms". We then take this as the PASS/FAIL criterion for any one combination of process materials. Typically we found the process combinations to yield results higher than 1 × 10¹⁰ Ohms, ensuring that the process chemistries could be used in combination.