Keywords
Citation
(1999), "VdL", Circuit World, Vol. 25 No. 3. https://doi.org/10.1108/cw.1999.21725cab.007
Publisher
:Emerald Group Publishing Limited
Copyright © 1999, MCB UP Limited
VdL
IPC
VdL
Keyword VdL
In May 1998 the CEOs of five European companies (AT&S, Fuba, Philips, Schweizer and STP), all members of the DRT (Directors Round Table), established by the chairman of the VdL, formed a working group with the aim of developing design rules for HDI boards (Table I and Figure 1).
Table IDesign rules for HDI cards (high density interconnection cards).All values are minimum values. High standard (not every company can fulfil all characteristics)
Symbol | Description | Standard | High standard |
A | Linewidth outerlayer | 0.125mm | 0.100mm |
A | Linewidth outerlayer Cu thickness < 25µm | 0.125mm | 0.100-0.075mm |
B | Spacing outerlayer | 0.125mm | 0.100mm |
B | Spacing outerlayer Cu thickness < 25µm | 0.125mm | 0.100-0.75mm |
C | Linewidth innerlayer Cu < 20µm | 0.100mm | 0.075mm |
D | Spacing innerlayer Cu < 20µm | 0.100mm | 0.075mm |
E | Mircrovia holesize | 0.125mm | 0.100-0.075mm |
F | Microvia landing pad | 0.30mm | 0.25mm |
G | Microvia pad | 0.30mm | 0.25mm |
H | Drill size buried hole | Max 0.30mm | 0.20mm |
I1 | Pad size buried hole outerlayer | 0.50mm | 0.50-0.40mm |
I2 | Pad size buried hole innerlayer | 0.70mm | 0.55mm |
J | Drill size plated through hole | 0.30mm | 0.20mm |
K1 | Pad six plated through hole outerlayer | 0.55mm | 0.5-0.40mm |
K2 | Pad size plated through hole innerlayer | 0.70mm | 0.55mm |
L | L/E (aspect ratio) microvia | ¾ 1 | ¾ 1 |
M | Min core thickness power/power | 0.100mm | 0.075mm |
M | Min core thickness signal/signal | 0.150mm | 0.100-0.075mm |
N | Core thickness (buried-multilayer) | Min 0.40mm | Min 0.30mm |
Max 0.80mm | Max 1.4mm | ||
Copper thickness plated through hole | 15µm | 13µm | |
Copper thickness buried hole | 15µm | 13µm | |
Copper thickness microvia | 10µm | 8µm | |
Basis materials | FR4 | FR4 Tg > 160°C | |
Material for HDI-layer | RCC, FR4 liquid dielectricum | RCC, FR4 liquid | |
dielectricum, with | |||
higher TG | |||
Number of HDI-layer | 1 of both sides | 2 of both sides | |
Board construction | Symmetrical | Symmetrical |
Figure 1 Dimensions for
constructing HDI cards
These design rules are intended to offer a common standard for microvia technologies. Designers employing this common standard will now be able to source boards from a variety of European manufacturers adhering to the new criteria.
The group decided to establish fundamental design rules for the Standard HDI. These rules reflect the capabilities of each member of the working group. In addition, the group has established a second column of "high standard" design rules.
Companies requiring copies of these special design rules should contact any of the member companies in the working group.
Future updates for both sets of rules are likely.
Book-to-bill
The VdL book-to-bill ratios are given in Figure 2 for December 1997-November 1998.
Figure 2 VdL-book-to-bill verhältnis
(ratios) December 97-November 1998