A room temperature 2 × 128 PtSi/Si-nanostructure photodetector array compatible with CMOS process

Abstract

Purpose

The purpose of this paper is to demonstrate a successful fabrication of 2 × 128 linear array of typical infrared (IR) detectors made of p-type tSi/porous Si Schottky barrier.

Design/methodology/approach

Using metal-assisted chemical etching (MaCE) as a unique approach, a sample definition of a porous Si nanostructure region for fabricating of any high-density photodetectors array has been formulated. Besides, the uniformity of pixels at different position along the array has been confirmed by optical images and measurements of photocurrent in IR regime at room temperature.

Findings

The experimental result illustrates the existence of an open-circuit voltage up to 30 mV at 1.5-μm wavelength for an area of 50 × 50 μm2. Additionally, this behavior is almost the same at different pixels of fabricated array.

Research limitations/implications

The uniformity of pixels and definition of nanostructure region are two most important challenges in fabrication of any high-density photodetectors array.

Practical implications

MaCE guarantees formation of reproducible, high-fidelity and controllable nanometer-size porous Si with well-defined and sharp edges of the patterned areas.

Originality/value

The proposed method offers a low-cost and simple process to fabricate high-density arrays of Schottky detectors which are compatible with the complementary metal-oxide semiconductor process.

Citation

Erfanian, A., Mehrara, H., Khaje, M. and Afifi, A. (2015), "A room temperature 2 × 128 PtSi/Si-nanostructure photodetector array compatible with CMOS process", Sensor Review, Vol. 35 No. 3, pp. 282-286. https://doi.org/10.1108/SR-11-2014-0736