Synaptic plasticity of TiO2 nanowire transistor
Microelectronics International
ISSN: 1356-5362
Article publication date: 3 February 2020
Issue publication date: 11 June 2020
Abstract
Purpose
The emulation of synapses is essential to neuromorphic computing systems. Despite remarkable progress has been made in the two-terminal device (memristor), three-terminal transistors evoke greater attention because of the controlled conductance between the source and drain. The purpose of this paper is to investigate the synaptic plasticity of the TiO2 nanowire transistor.
Design/methodology/approach
TiO2 nanowire transistor was assembled by dielectrophoresis, and the synaptic plasticity such as paired-pulse facilitation, learning behaviors and high-pass filter were studied.
Findings
Facilitation index decreases with the increasing pulse interval. A bigger response current is obtained at the pulses with higher amplitude and smaller intervals, which is similar to the consolidated memory at the deeply and frequently learning. The increased current at the higher stimulus frequency demonstrates a promising application in the high-pass filter.
Originality/value
TiO2 nanowire transistors possess broad application prospects in the future neural network.
Keywords
Acknowledgements
This work is supported by Natural Science Foundation of Jiangsu Province of China (Grant No. BK20171166).
Citation
Qi, H. and Wu, Y. (2020), "Synaptic plasticity of TiO2 nanowire transistor", Microelectronics International, Vol. 37 No. 3, pp. 125-130. https://doi.org/10.1108/MI-08-2019-0053
Publisher
:Emerald Publishing Limited
Copyright © 2020, Emerald Publishing Limited