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Evaluation of fan-out wafer level package strength

Cheng Xu (School of Mechanical and Aerospace Engineering, Nanyang Technological University, Singapore)
Z.W. Zhong (School of Mechanical and Aerospace Engineering, Nanyang Technological University, Singapore)
W.K. Choi (School of Mechanical and Aerospace Engineering, Nanyang Technological University, Singapore)

Microelectronics International

ISSN: 1356-5362

Article publication date: 1 March 2019

Issue publication date: 21 May 2019

139

Abstract

Purpose

The fan-out wafer level package (FOWLP) becomes more and more attractive and popular because of its flexibility to integrate diverse devices into a very small form factor. The strength of ultrathin FOWLP is low, and the low package strength often leads to crack issues. This paper aims to study the strength of thin FOWLP because the low package strength may lead to the reliability issue of package crack.

Design/methodology/approach

This paper uses the experimental method (three-point bending test) and finite element method (ANSYS simulation software) to evaluate the FOWLP strength. Two theoretical models of FOWLP strength are proposed. These two models are based on the location of FOWLP initial fracture point.

Findings

The results show that the backside protection tape does not have the ability to enhance the FOWLP strength, and the strength of over-molded structure FOWLP is superior to that of other structure FOWLPs with the same thickness level.

Originality/value

There is ample research about the silicon strength and silicon die strength. However, there is little research about the package level strength and no research about the FOWLP strength. The FOWLP is made up of various materials. The effect of individual component and external environment on the FOWLP strength is uncertain. Therefore, the study of strength behavior of FOWLP is significant.

Keywords

Acknowledgements

The financial support to this research is provided by the Industrial Postgraduate Programme research grant of Economic Development Board (EDB), Singapore. The authors are grateful for the support of EDB Singapore and STATS ChipPAC Ltd.

Citation

Xu, C., Zhong, Z.W. and Choi, W.K. (2019), "Evaluation of fan-out wafer level package strength", Microelectronics International, Vol. 36 No. 2, pp. 54-61. https://doi.org/10.1108/MI-06-2018-0040

Publisher

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Emerald Publishing Limited

Copyright © 2019, Emerald Publishing Limited

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