A novel addressing algorithm of radix-2 FFT using single-bank dual-port memory
ISSN: 0305-6120
Article publication date: 15 December 2020
Issue publication date: 3 January 2022
Abstract
Purpose
This paper aims to present a single-block memory-based FFT processor design with a conflict-free addressing scheme for field-programmable gate arrays FPGAs with dual-port block memories. This study aims for a single-block dual-port memory-based N-point radix-2 FFT design that uses memory locations and spending minimum clock cycle.
Design/methodology/approach
A new memory-based Fast Fourier Transform (FFT) design that uses a dual-port memory block is proposed. Dual-port memory allows the design to perform two memory reads and writes in a single clock cycle. This approach achieves low operational clock and smallest memory simultaneously, excluding some small overhead for exceptional address changes. The methodology is to read from while writing to a memory location, eliminating the need for excess memory and additional clock cycles.
Findings
With the minimum memory size and the simplest architecture, radix-2 FFT and single-memory block are used. The number of clock pulses spent for all FFT operations does not provide much advantage for low-point FFT operations but is important for high-point FFT operations. With the developed algorithm, N memory is used, and the number of clock pulses spent for all FFT stages is (N/2 +1)log2N for all FFT operations.
Originality/value
This is an original paper, which has simultaneously in whole or in part been submitted anywhere else.
Keywords
Acknowledgements
This work was supported in part by the Eskişehir Osmangazi University Research Projects Commission under Grant 201615022.
Citation
Kaya, Z. and Seke, E. (2022), "A novel addressing algorithm of radix-2 FFT using single-bank dual-port memory", Circuit World, Vol. 48 No. 1, pp. 64-70. https://doi.org/10.1108/CW-06-2020-0108
Publisher
:Emerald Publishing Limited
Copyright © 2020, Emerald Publishing Limited